The heart of G8PP is a 5V in-situ programmable CPLD. I use Altera EPM7128S because I'm familiar with it, there may well be other suitable CPLD. EPM7128 has enough logic to solve a nagging problem with the processors of the 1970's, i.e. how to simplify the bootstrap operation? The traditional bootstrap device is the ROM which needed to be programmed on a separate programmer; ROM also takes up extra board space and may reside in system memory that needs to be writable for operating software (an example is both CP/M and boot ROM use page 0). Developing a working boot ROM is a slow, tedious process. Life is so much easier if bootstrap code can be loaded into memory just like other software.
EPM7128 implements the serial bootstrap function with a simple serial port and DMA controller that, when enabled at power up, take over the processor bus and transfer 256 bytes of data from serial port to boot area of memory. When the 256th byte of data is received, the processor is released to execute the code just loaded. The bootstrap code is typically a simple file loader that loads more sophisticated monitor/debugger into memory. In order not to reload the software every power cycle, the RAM is battery-backed. The bootstrap and monitor/debugger are also stored in protected area of memory that can be switched out during normal operation.
Here are the key functions of G8PP:
- A programmable logic of sufficient complexity to support address decode and basic I/O. Programmable logic is needed because different processors have control signals with different functions and timings requirements. Altera EPM7128S is selected because it is a medium complexity 5V programmable logic that is still available.
- A serial port with associated support logic that will perform the “Serial Bootstrap” function. This function, when enabled at power up, will receive a pre-determined number of serial data and store them in designated RAM locations. The support logic will tri-state the target processor's bus during serial bootstrapping. When the pre-determined number of data have received, the support logic will release the target processor to run. The serial bootstrap functionality is small enough to fit in the existing CPLD.
- A battery-backed RAM that's large enough to fill the memory space of 8-bit processor plus extra memory to hold bootstrap code in nonvolatile memory banks. The traditional bootstrap code and monitor software resided in ROM are loaded and stored in the nonvolatile memory banks instead. This method simplifies the decoding of memory, reduces bus loading, and speeds up monitor software development cycle. The banked memory write-protect the bootstrap and monitor software and also give the application software complete control of the processor's memory space.
- A 8-bit wide compact flash interface for mass storage.
- A 48-pin 600-mil prototype socket for 5V 8-bit microprocessors from 1970's and 1980's. They include 680x, Z80, 8085 and 6502. 16-bit processors that can operate in 8-bit mode are also included such as 68008 and 32008. These processor are generally available in 40-pin or 48-pin DIP package that can plug directly into the prototype socket. The prototype socket has wiring pads to connect addresses, data, and control signals to the corresponding wiring pads on CPLD and RAM.
- RC2014 bus interface so the target processor can access the large number of RC2014 I/O modules.
G8PP has two modes of operation as determined by the Bootstrap jumper at power up:
- UART Bootstrap At power up the target processor is held in idle state until 255 bytes of instruction is uploaded to UART (115200 baud, N81, no handshake) which is then copied to memory starting from location 0x0. Afterward the CPU starts execution from 0x0. This is the mode to load programs into the non-volatile RAM prior to booting via the RAM bootstrap mode.
- RAM Bootstrap This is normal mode of operation. At powerup, the target processor fetches program from physical location 0 which contains the bootstrap monitor. The bootstrap monitor write protect physical page 0 where bootstrap monitor resides. It then makes a copy of itself to 0xB000-0xBFFF and jump to it. Lastly the physical page 0 is replaced with logical page 0 which mapped to different physical page. This way the physical page 0 containing the bootstrap monitor is write protected and moved out of way. The application program will have unfettered access to all 64K space of the target processor.