Building a 22MHz Z80 Computer in 4 Stages

Step-by-step instruction on building a high-performance, CP/M-ready, expandable Z80 computer

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This project starts with a simple Z80 design with 4 integrated circuits and build it up in stages into a high performance, sophisticated Z80-based system. The Z80 computer is functional in each stage, more functionalities are added in each subsequent stages. The goal is a high-performance, expandable, CP/M capable Z80 system. This Z80 design is based on Z80SBC64.

Outline of the project:

  • Bill of materials,
  • schematic,
  • pc board gerber photoplot files,
  • CPLD programming file

Stage 1 hardware

  • step-by-step construction
  • program the CPLD, populate the RAM, Z80, oscillator
  • power up

Stage 1 software

  • Z80Mon
  • SCMonitor

Stage 2 hardware

  • Add DS1210 and battery

Stage 2 software

  • protected bootstrap monitor
  • rudimentary CP/M

Stage 3 hardware

  • Add CF interface

Stage 3 software

  • CP/M

Stage 4 hardware

  • Add RC2014 connector

Stage 4 software

Z80SBC64 EPM7064 Programming file

x-zip-compressed - 1.10 kB - 02/10/2019 at 01:42


Bill of material Z80SBC64_r0.pdf

Z80SBC64 Bill of Materials

Adobe Portable Document Format - 38.25 kB - 02/10/2019 at 01:41



Z80SBC64 schematic

Adobe Portable Document Format - 30.98 kB - 02/10/2019 at 01:40


Z80SBC64 Gerber photo plots, rev 1

x-zip-compressed - 22.82 kB - 02/10/2019 at 01:39


  • Z80SBC64 Theory of Operation

    Plasmode9 hours ago 0 comments

    Z80SBC64 has two modes of operation as determined by the Bootstrap jumper at power up (see the last picture of the previous project for location of bootstrap jumper).

    Serial Bootstrap

    At power up Z80 processor is tri-stated waiting for 255 bytes of instruction is be uploaded to the serial port (115200 baud, N81, no handshake) which is copied to memory starting from location 0x0. When the 255th byte of data is received and copied to memory, the CPLD state machine release Z80 to run from location 0x0.  The 255-byte code can be any software such as hardware diagnostic, but is normally a simple file loader to load more sophisticated application software.  In this stage, it is a simple Intel Hex loader, Z80SBCLD.BIN that loads a monitor/debugger and executes it at the completion of file load.

    RAM Bootstrap

    This is normal mode of operation.  At power up, Z80 fetches program from physical location 0 which contains the bootstrap monitor. The bootstrap monitor write-protect physical page 0 where bootstrap monitor resides. It then makes a copy of itself to 0xB000-0xBFFF and jump to it. Lastly the physical page 0 is replaced with logical page 0 which mapped to different physical page. This way the physical page 0 containing the bootstrap monitor is write protected and moved out of way. The application program will have unfettered access to all 64K space of the target processor.

    Memory Map
    Z80SBC64 has 128KB of RAM which is divided into 4 banks of 32KB each.  At any time only 2 banks (64KB) are accessible by Z80.  Bank 1 is always at the upper 32KB memory (0x8000-0xFFFF), it is the common memory that can not be switched out.  The lower 32KB can be switched between bank 0, 2, and 3 by writing 0x0, 0x2, and 0x3, respectively, to the bank register.  At reset the lower 32KB is always mapped to bank 3.  Bank 3 contains the bootstrap monitor code that copies itself to upper 32KB and switch bank 0 into the lower 32KB, thus protect the content of bank 3 from other programs.

    I/O Map
    Bank Register is located at I/O space 0x1F.  It is a write-only register, a read will get random value.  Only the least significant 2 bits of the Bank Register are used, the upper 6 bits are "don't care".  At reset the content of bank register is set to 0x3 which maps bank 3 to the lower 32KB.  Bank 3 is reserved for the bootstrap monitor and system software.  Writing 0x2 will map bank 2 to the lower 32KB of memory space.  Bank 2 is normally used by CP/M 3.  Writing 0x0 will map bank 0 to the lower 32KB of the memory.  Bank 0 is the default bank after the bootstrap monitor completes the booting process.

    Compact flash is located at I/O space 0x10-0x17.
    0x10    CF Data Register
    0x11    CF Error Register (read), Feature Register (write)
    0x12    CF Sector Count Register
    0x13    LBA Low, LBA(7:0)
    0x14    LBA Mid, LBA(15:8)
    0x15    LBA High, LBA(23:16)
    0x16    Device Register, LBA(27:24)
    0x17    CF Status (read) and Command (write) Register

    Serial port is located at I/O space 0xF8-0xF9.
    0xF8    Serial Status Register
        bit 0 is RxReady flag.  bit 0 is high when receive data is ready.  cleared to zero when the received data is read.
    0xF9    Serial Transmit (write) and Receive (read) register.  When write to 0xF9, TX pin of the CPLD is equal to the value of d(0) (bit 0) of the data.  d(7:1) are "don't care".  The serial port has no interrupt capability and no handshake.  It is hardwired to 8 data bit, 1 stop bit and no parity.  The baud rate is CPU clock /192.  e.g., 22.1184MHz CPU clock results in 115200 serial clock.

  • Stage 1 Hardware, Building A Minimal Z80 Computer

    Plasmode7 days ago 0 comments

    In the first stage we'll build a very simple yet functioning Z80 computer with just 4 integrated circuits, plus resistors,  capacitors and hardware.  The bill of materials is included in the Files Section.  In stage 1 the following items will be assembled:

    U1Z84C0020PEGMouser 692-Z84C0020PEG
    U3128Kx8 Static RAMMouser 913-AS6C1008-55PCN
    U422MHz oscillator
    R154.7K 8-pin SIP BusJameco 1970367
    R1-4, R8-9, R16
    4.7K, 1/8W
    C3-80.1uF bypass
    S1Push button SPSTJameco 149948
    J12.1mm x 5.5mm Power
    Jameco 101178
    T343-pin header
    P21x6 right angle female
    P32x5 header

    The pc board artwork is included in the FIles Section, so is the schematic of Z80SBC64 and the Altera EPM7064 programming file.

    Here are step-by-step pictorial assembly guides for building a minimal Z80 computer.  The order of assembly is based on the height of the components, the lowest components are soldered down first and the tallest last.  In the first picture, all resistors (4.7K), bypass capacitor (0.1uF), and SIP resistor (4.7K BUS) are soldered down.  Orientation of SIP resistor is important, pin 1 is marked with a black bar and oriented where the red arrow is pointed.

    In the second picture, the IC sockets are installed as well as the 1x6 serial port header.

    In the third picture, the PLCC socket is installed.  The orientation of the socket is important, the beveled corner should be placed where the red arrow is pointed.  1x3 jumper block (T34), 2x5 programming header (P3), push button (S1), and 2.1mm x 5.5mm power jack (J1) are also installed. 

    The fourth picture shows the solder side of the pc board.  Because the reset supervisor, U5, is not yet installed, a 4.7K pull up resistor from nRESET to VCC is required to negate the nRESET signal.  Please note, U5 may be optionally installed in this stage.  If U5 is installed, then the pull-up resistor is not required. 

    The 1st stage assembly is now completed.  The board should be cleaned with isopropyl alcohol and dried before installing components.

    In the fifth picture the Altera EPM7064SLC44 is installed.  Observe the orientation of the part, the beveled side with dimple in the middle must be aligned with the red arrow.  Program the EPM7064 with USB Blaster, line up the pin 1 of USB Blaster cable (red strip) with the pin 1 of 2x5 header (pointed by a red arrow).

    The last picture shows how the remaining integrated circuits are installed.  Observe the orientation of the components.  Also install the jumper to 'serial bootstrap' position as shown with a red arrow.  Install two jumpers across pin1 & pin8 of U6 and across pin5 & pin6 of U6.  The board is now populated and ready for power.

  • Introduction to Z80SBC64

    Plasmode02/09/2019 at 01:21 0 comments

    The z80 design is based on Z80SBC64, the '64' refers to Altera EPM7064, but as many Z80 SBC that must had been built over the years, this can easily be the 64th Z80 SBC.  The current trend in low chip-count Z80 SBC is using another processor to provide bootstrap function as well as I/O functions for the Z80.  Such dual-processor architecture requires complex software interaction between the two processors, and the combined throughput of the two processors are less than the throughput of any one of the processors, so it feels like stepping backward in performance and the hardware/software seems harder to comprehend and to modify.  I prefer the traditional computer architecture where Z80 controls everything around it but does it faster and with fewer chips.  The key is using programmable logic instead of TTL logic, but instead of the expensive FPGA that requires 5V-to-3.3V translation, using the low-cost 5V complex programmable logic device (CPLD).  Furthermore, the CPLD has sufficient logic to implement an unusual feature, serial bootstrap, that uses serial port to load the traditional ROM code in RAM resulting in a ROM-less computer.  The ROM-less design eliminates the hassle of ROM programming and further reduces the chip count resulting in a small 2" x 4" pc board.

    The original design was prototyped with Altera EPM7128S CPLD, a 100-pin surface mount device that is difficult for most hobbyists to assemble.   Further design refinements allow the final design to fit in a EPM7064S as 44-pin PLCC package.  By hosting the PLCC device in a through-hole PLCC socket, the pc board can be assembled by most hobbyists.  The final Z80SBC64 design is proven with successful construction and operation of 10 or more boards.

    The four-stage approach is originally conceived to simplify the assembling and testing process where the partially assembled board can be functionally tested in each stage.  This approach is particularly suited for hobbyists putting together a new board.  It is reassuring to take baby steps and verify things are working in each step.  Another issue is parts ordered may not be available or delivered, but we like to play with the partially assembled system without all the parts.  Furthermore, I believe the learning process is enhanced as limitations and capabilities of the computer at each stage are explored and we learn how new features added in next stage enhances the existing capabilities.

    Each of the 4 stages are breakdown into hardware phase and software phase.  The hardware is the assembly phase, and the software is the testing and exploration phase.  The computer is functioning at each stage and gains sophistication as the assembly progresses.  It is not necessary to finish all 4 stages of assembly.  The computer is functioning and may be perfectly suited for certain applications without reaching the end of stage 4. 

    Here are brief descriptions of the four stages:

    • Stage 1, minimal operating Z80, runs native monitor, SCMonitor, BASIC programs, games
    • Stage 2, software are preserved between power cycles, banked memory hardware protects system software from application software.
    • Stage 3, compact flash interface and CP/M
    • Stage 4, RC2014 expansion bus, interface to RC2014 compatible boards

    While the board is capable of 22 MHz operation, it is not necessary to run at 22Mhz.  If only slower Z80, RAM and oscillator are available, it is perfectly fine to run the board at the lower clock frequency.  The serial port baud rate is directly determined by the CPU clock, the table below show the relationship between clock frequency, serial baud, and RAM speed:

    Clock Frequency
    Serial Baud
    RAM access time
    slow RAM
    slow RAM

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