Z80SBC64 Theory of Operation

A project log for Building a 22MHz Z80 Computer in 4 Stages

Step-by-step instruction on building a high-performance, CP/M-ready, expandable Z80 computer

plasmodePlasmode 02/16/2019 at 16:410 Comments

Z80SBC64 has two modes of operation as determined by the Bootstrap jumper at power up (see the last picture of the previous project for location of bootstrap jumper).

Serial Bootstrap

At power up Z80 processor is tri-stated waiting for 255 bytes of instruction is be uploaded to the serial port (115200 baud, N81, no handshake) which is copied to memory starting from location 0x0. When the 255th byte of data is received and copied to memory, the CPLD state machine release Z80 to run from location 0x0.  The 255-byte code can be any software such as hardware diagnostic, but is normally a simple file loader to load more sophisticated application software.  In this stage, it is a simple Intel Hex loader, Z80SBCLD.BIN that loads a monitor/debugger and executes it at the completion of file load.

RAM Bootstrap

This is normal mode of operation.  At power up, Z80 fetches program from physical location 0 which contains the bootstrap monitor. The bootstrap monitor write-protect physical page 0 where bootstrap monitor resides. It then makes a copy of itself to 0xB000-0xBFFF and jump to it. Lastly the physical page 0 is replaced with logical page 0 which mapped to different physical page. This way the physical page 0 containing the bootstrap monitor is write protected and moved out of way. The application program will have unfettered access to all 64K space of the target processor.

Memory Map
Z80SBC64 has 128KB of RAM which is divided into 4 banks of 32KB each.  At any time only 2 banks (64KB) are accessible by Z80.  Bank 1 is always at the upper 32KB memory (0x8000-0xFFFF), it is the common memory that can not be switched out.  The lower 32KB can be switched between bank 0, 2, and 3 by writing 0x0, 0x2, and 0x3, respectively, to the bank register.  At reset the lower 32KB is always mapped to bank 3.  Bank 3 contains the bootstrap monitor code that copies itself to upper 32KB and switch bank 0 into the lower 32KB, thus protect the content of bank 3 from other programs.

I/O Map
Bank Register is located at I/O space 0x1F.  It is a write-only register, a read will get random value.  Only the least significant 2 bits of the Bank Register are used, the upper 6 bits are "don't care".  At reset the content of bank register is set to 0x3 which maps bank 3 to the lower 32KB.  Bank 3 is reserved for the bootstrap monitor and system software.  Writing 0x2 will map bank 2 to the lower 32KB of memory space.  Bank 2 is normally used by CP/M 3.  Writing 0x0 will map bank 0 to the lower 32KB of the memory.  Bank 0 is the default bank after the bootstrap monitor completes the booting process.

Compact flash is located at I/O space 0x10-0x17.
0x10    CF Data Register
0x11    CF Error Register (read), Feature Register (write)
0x12    CF Sector Count Register
0x13    LBA Low, LBA(7:0)
0x14    LBA Mid, LBA(15:8)
0x15    LBA High, LBA(23:16)
0x16    Device Register, LBA(27:24)
0x17    CF Status (read) and Command (write) Register

Serial port is located at I/O space 0xF8-0xF9.
0xF8    Serial Status Register
    bit 0 is RxReady flag.  bit 0 is high when receive data is ready.  cleared to zero when the received data is read.
0xF9    Serial Transmit (write) and Receive (read) register.  When write to 0xF9, TX pin of the CPLD is equal to the value of d(0) (bit 0) of the data.  d(7:1) are "don't care".  The serial port has no interrupt capability and no handshake.  It is hardwired to 8 data bit, 1 stop bit and no parity.  The baud rate is CPU clock /192.  e.g., 22.1184MHz CPU clock results in 115200 serial clock.