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enhancement to depletion

DIY method to lower gate threshold voltage of regular MOSFETs, ultimately reversing it.

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I've been passively trying to get some depletion mode power mosfets, mainly for making LED torches (flashlights) with adjustable brightness. They are useful because I can make a source follower with zero or negative voltage drop, the output of which can easily go up to the very rail without needing a bootstrap. But I couldn't get them. They are rare and quite expensive, and no one seems to have them in stock. I maybe could have obtained them, but I wasn't desperate enough...

Lately, I was reading a book about semiconductor junctions. Particularly, a section about MOSFETs, and about flash memory. I saw a picture of a flash memory mosfet with no floating gate, and an idea popped up. What if I can get analogous effect on a regular mosfet, that can effectively convert a typical enhancement mode mosfet into a depletion-mode mosfet? Hmm!

What is depletion mode, and why you might want it

Enhancement MOSFET: normally off (the common stuff). Depletion MOSFET: normally on. To switch off an n-channel depletion MOSFET, you should apply negative voltage to gate terminal. That is, it behaves exactly the same as an enhancement n-channel, but it has negative gate threshold voltage. Very similar to a vacuum tube, by the way.

In other words, depletion MOSFET is equivalent to enhancement mosfet with built-in biasing (voltage source in series with gate terminal).

Depletion mosfets are quite rare. Chances of finding one with specs you need are much lower, and depletion mosfets are usually substantially more expensive than enhancement ones.

A JFET is a more common example of a depletion mode FET. But power JFETs are rare beasts, again.

Depletion MOSFETs are not as useful as enhancement ones, but there are a few applications where they are super handy.

One is a voltage follower with zero or negative voltage drop. With just two components (mosfet + potentiometer), one can make a very simple knob power adjustment, that has almost zero dropout at max, and infinite input resistance. It can be used as a quick-n-dirty fan speed adjustment, LED brightness regulator, etc. See this project log for a demo of such regulator.

How to?

Modifying!

To change the MOSFET, all you need is to feed constant current into gate terminal of the MOSFET.

It will take around +40 V / -25 V at gate terminal or the current to start. Because it’s a deliberate violation of absolute maximum ratings of the MOSFET, I call it “torture”.

In both cases, threshold voltage goes down. Positive torture begins to change the transistor immediately, but the negative torture has a kind of lag. This lag seems to be some stray leakage that has to be overcome. The gate voltage rises to about 40 V during that lag. Also, negative torture requires more current, it can reach deeper depletion, and does not reverse direction.

So far, I was not able to make threshold voltage to increase. From that, I think that making depletion mode p-channel mosfets might be impossible (but I haven’t tried yet!).

The indicated torture currents are for Infineon IPD10N03LA mosfet, which is an n-channel enhancement mode MOSFET with on-resistance of 10.4 mΩ, 25 V max drain-source voltage, gate charge of 8.2 nC. No extensive tests on other mosfets were done so far, but I would suggest to scale torture currents in proportion to gate charge of your transistor.

@RoGeorge had successfully modified BUZ11A with positive torture, but didn’t do it in a controlled manner. See his project, #Your MOSFET is not good enough? Then modify it!.

If you successfully modify a MOSFET, let me know! (post a comment). Eventually, I hope to make a table of MOSFETS that can/can’t be modified, and torture parameters required.

Reverting!

It is possible to undo the modification to a large extent, by applying positive voltage to gate. The voltage should be large, but slightly smaller than one required to cause torture leakage current. For IPD10N03LA, +35V seems to be the sweet spot.

Real-time threshold monitoring

Wondering how did I get these plots?

I made two circuits for torturing MOSFETs with real-time control of gate threshold voltage. Both circuits are chopping: the mode of operation is cyclically switched between measuring threshold and torturing.

* “blink torture” circuit – simple, but only for negative torture. Was all-right for initial proof-of-concept.

* “experimentorture” circuit – with precise threshold measurement, supporting both positive and negative torture.

Drawbacks

Sounds too good to be true? Sure, there are some problems with this conversion.

* after torture, the mosfet drifts back substantially. This drift settles out after a day or so, with substantial fraction of modification remaining. Long-term stability of the modification is unknown. However, quite surprisingly, the modification can survive soldering temperatures. ...

Read more »

TORTURE2.TXT

raw kinetic for https://hackaday.io/project/16384-enhancement-to-depletion/log/48281-redoing-last-experiment

plain - 29.79 MB - 10/29/2016 at 10:34

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unrelated - my torch.png

before having depletion mode mosfets, I used to make a torch like this.

Portable Network Graphics (PNG) - 44.40 kB - 10/28/2016 at 21:43

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  • 1 × smoothly adjustable low voltage power supply for threshold voltage testing; I used Li-ion cell + pot
  • 1 × smoothly adjustable medium voltage floating power supply should go up to 50 volts. Current required is extremely low.
  • 1 × relay Power Supplies / Uninterruptible Power Supplies (UPS)
  • 1 × signal generator Arduino will do
  • 1 × MOSFET to convert/sacrifice

View all 8 components

  • Does modified mosfet survive soldering?

    DeepSOIC11/01/2016 at 18:27 0 comments

    Yes it does!

    First heating did change threshold voltage noticeably. Further annealing didn't do much at all.

  • undoing depletion mode

    DeepSOIC10/30/2016 at 20:10 0 comments

    From positive voltage torture kinetic, I though that positive voltage might be doing two things at the same time: change gate threshold voltage, and undo the changes. Because the timelapse looks like this: first, threshold voltage goes down, then it turns around and goes up and essentially returns to where it had started.

    So I decided to use it to restore the lowered threshold by applying large positive voltage, that is large, but just a little smaller than what is needed to make the gate leak, and the threshold start to o down.

    It works!

    On this timelapse:

    First, I reduced the threshold voltage of a mosfet by applying large negative voltage (23-36V, I actually was pulling a current). Then, I applied positive voltage. This caused threshold to rise.

    ---------

    I also seems to have successfully restored a mosfet tortured to the end with positive current, here. That mosfet was behaving bad. When I inserted it into gate threshold measuring circuit, it drifted like crazy. After feeding +35V to gate for a few hours, its threshold didn't change much. But it doesn't do that awful drifting anymore!

  • the previous "leaky" mosfet likely wasn't leaky!

    DeepSOIC10/29/2016 at 19:05 0 comments

    I started reproducing the negative voltage torture with a new mosfet, and it is the same! Well, I didn't measure the actual torture curve. I just found out that it is the same 20-ish volts it takes to observe gate leakage. Either this mosfet is leaky too, or it is just the way it is. Strange.

    So I stopped the attempt to reproduce, and will save this LAST mosfet for something more interesting.

  • negative torture current

    DeepSOIC10/29/2016 at 15:49 0 comments

    Apparently, the mosfet has a leaky gate. Current of 0.1 uA takes less than usual voltage (-26 V), and only at 10 uA (50% duty) gate threshold began to change.

    The process that followed is quite interesting. It ended with an almost killed mosfet. Gate-to-source now measures about 140 KOhm.

    Interesting is that it started very slowly, then accelerated, and then slowed down and stopped.

    This seems to be a slightly dodgy mosfet, so I won't do any further analysis of it. UPDATE: no, it is an all-right MOSFET.

    UPDATE: attempt to recover it with +35V finished it off. This MOSFET is now a dead short across all 3 pins.

  • Current mode torture analysis (positive voltage)

    DeepSOIC10/29/2016 at 13:37 0 comments

    Overall torture kinetic

    Slopes

    Rate of threshold voltage change is not exactly proportional to gate current, but close to being so.

    Post-torture drift

    Surprisingly little drift. But the mosfet is likely very much damaged, so it doesn't make much sense.

    ----

    I have only one more fresh mosfet remaining for experimenting (same model, IPD10N03LA). I plan doing a negative voltage torturing for comparison with positive. After that, I either order more of them (if I can), or move to experimenting with other mosfet models.

    UPDATE: found one more!

  • redoing last experiment

    DeepSOIC10/28/2016 at 20:50 1 comment

    In progress now. So far, it is going rather similarly to a previous one, even though that previous one was done on defunct circuit.

    The threshold voltage is now rising again.

    .....

    UPDATE: finished.

    Unprocessed data available in files: TORTURE2.TXT. Note: torture currents are chopped with 50% duty cycle, so the average currents into gate are half the indicated values.

    Kinda similar to what I got with broken circuit. Except, this time:

    * fresh transistor

    * final current was 1 uA, not 0.3 uA

    * I almost reached the end of the process =)

  • Epic fail

    DeepSOIC10/28/2016 at 19:19 0 comments

    Today I wanted to do another experiment with next mosfet. Only to find out that my experimentorture circuit is measuring some nonsense. DOH!

    It turns out that I've blown the TL431 ic when setting up the datalogger, and it is a dead short in all directions. This means my previous experiment is completely and totally broken, and I will put a note there right now.

    Arrrgh!

    That mosfet apparently was tortured to near death, with gate threshold voltage (1 mA) measuring 0.708 V, and with substantial conductivity at zero gate voltage.

  • Current mode torture analysis [wrong - done on blown circuit!]

    DeepSOIC10/28/2016 at 12:13 1 comment

    As I found out earlier, the rate of MOSFET modification was very sensitive to torture voltage. Like, at 38 V it was barely progressing, but at 42 V it was pretty fast.

    I thought that if I control current, the rate of change would be more predictable. And indeed, if I take the initial rates of change, they seem pretty proportional to current:

    Except that for the first point, at torture current of 0.01 uA, I essentially didn't detect any effect at all. It might be because the current was not actually delivered to the mosfet gate (it may have leaked through the switch for example (see circuit), although I checked switch leakage beforehand). Or it was because the mosfet wasn't completely fresh... Anyway, there's not enough points to draw major conclusions yet...

    And as you already know, this initial rate thing doesn't tell the whole story, as the threshold voltage ceases decreasing and starts to increase at later time.

    Curious to see, what will happen for negative torture. Also curious to see if transfer characteristic is any different to what I got before.

  • "experimentorture" circuit

    DeepSOIC10/28/2016 at 00:26 5 comments

    This is the new circuit for torturing mosfets. The switches are actuated out of phase. As I explained earlier, the switches are now solid state (pairs of MOSFETs driven through photovoltaic optoisolator).

  • this is a crazy surprise generator project! [wrong - done on blown circuit!]

    DeepSOIC10/27/2016 at 23:46 1 comment

    I have made my experimentorture circuit, and right now I'm torturing a MOSFET with a positive voltage, feeding 0.3 uA of current into gate at 50% duty cycle (2.5 s of current, then 2.5 s of gate threshold measurement).

    Gate threshold voltage (for Ids = 1 mA) was going down. Then it kinda stopped at around -0.5V. But I decided to no stop the process, and it started to go UP!!! Isn't it fascinating!

    I have datalogging now, so I will post a plot when I finish it.

    measurement in a mess...

    UPDATE. The mosfet has changed back into enhancement mode... probably... , with gate voltage for 1 mA at about +0.25 V. It's too late now, so I have to stop the torture. I leave threshold to datalog overnight. With 13 SPS recording rate, it's going to be a big file.

    UPDATE: the plot!

    I started with 0.01 uA of torture current. No effect. Increased to 0.1 uA. Saw something. Increased to 0.3 uA. Now we are talking! Somewhere close to minimum, I was thinking to increase the current further, but changed my mind. Glad I did!

    The wiggles on rising part are caused by me tweaking the torture current, which was reducing a little bit (the tweaks were like 0.28 -> 0.3 uA). The very fact it was reducing is interesting by itself, as it must be gate voltage going up.

    I failed to stop the torture cleanly, oops! Nothing serious, though.

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Discussions

lienmeister wrote 11/02/2016 at 14:01 point

Sounds like you are trapping surface state electrons.   Fets are a voltage control device and usually have a high impedance so there is limited conduction into the gate.   If you hit the gate with enough voltage you can get some conduction and the electrons get trapped below the gate in the SiO2 insulator.

  Are you sure? yes | no

DeepSOIC wrote 11/02/2016 at 14:59 point

I would really doubt that surface states have anything to do here. Because surfaces in this case are interfaces between an insulator and a conductor/semiconductor. Surface states of semiconductor can't have large activation barriers for recharging, thus it should be easy to reset with heat.

Surface states of insulator can, but they will readily tunnel out into semiconductor/metal, so again, thermal equilibrium should be established easily.

If the torture creates new surface states that didn't exist before, I would call them "defect states on surface". Can be the case...

  Are you sure? yes | no

Torrid Luna wrote 10/31/2016 at 21:34 point

The DN and LND series Depletion Mosfets from Microchip Technologies are readily available and inexpensive (<1 USD per piece).

  Are you sure? yes | no

DeepSOIC wrote 11/01/2016 at 09:08 point

Great, but can you please point me to a depletion mosfet that has on-resistance of less than 0.5 ohms? So far all I saw was 25 ohms, not useful.

Or maybe they are hidden from russia...

  Are you sure? yes | no

RoGeorge wrote 10/29/2016 at 21:38 point

From your latest charts, https://hackaday.io/project/16384/log/48309, my understanding is that the transistor is slowly recovering after altering its datasheet threshold Vgs voltage (by pushing or pulling a high current through the gate). So, the change of threshold voltage slowly came back to its datasheet value by itself. Is this correct?

I am asking because the transistor I modified last week seems to keep its modified gate threshold voltage. For my transistor, no recovery can be observed during the last few days. All these days I didn't have time for it, so the transistor was not connected, only measured once a day: https://hackaday.io/project/16616/log/48067

  Are you sure? yes | no

DeepSOIC wrote 10/29/2016 at 22:23 point

No, it returned under torture! But I think the returning back to factory Vgth is a coincidence. 

  Are you sure? yes | no

BotLawson wrote 10/28/2016 at 21:00 point

Apparently not all is lost for finding high power J-fets.  I've run across several silicon-carbide power J-fet while researching high voltage switching circuits.  https://www.google.com/search?q=SiC+j-fet&ie=utf-8&oe=utf-8 

There are ways to achieve this effect in circuit.  Add a mini-battery with parallel capacitor in series with the mosfet gate.  PCB mount coin cells get quite small and with essentially zero average gate current, life time should be years or more.  Alternatively photo-voltaic opto-isolators can supply 2-4uA at 5-10V to anywhere in a circuit when driven by 5-20mA.  Got a circuit I've been meaning to test that takes advantage of PV opto-isolators to bias a FET source follower.  

  Are you sure? yes | no

DeepSOIC wrote 10/28/2016 at 21:25 point

Silicon carbide jfets? Interesting, thanks for info!

Mini-battery will most likely do the trick indeed. As will a super-cap, and maybe even a very low leakage regular cap. The trick then will be to isolate it really well.

  Are you sure? yes | no

DeepSOIC wrote 10/28/2016 at 21:47 point

What also works is to use a mosfet as a low side switch, and connect its gate to potentiometer.


The main problem with this configuration is that active range on the pot is narrow, making it a bit hard to adjust. But it still features that dramatic dynamic range of brightness adjustment. 

EDIT: I have a torch like that in my pocket =)

  Are you sure? yes | no

Yann Guidon / YGDES wrote 10/29/2016 at 01:37 point

I've used that system for a long while, and others for even longer, I suppose :-)

  Are you sure? yes | no

esot.eric wrote 10/22/2016 at 03:31 point

Very interesting. Been a *long* time since I took those classes in MOSFETs, but I vaguely remember wondering whether something like this is possible. The images of the MOSFETs in my book were slightly different, showing a diagonal slope between the drain and source, the "conduction-channel"(?). Here's something like what I remember...


I'm curious, your original mosfet was N-Channel enhancement-mode, right? Is your new "depletion-mode" transistor equivalent, then, to a P-Channel depletion-mode?

Also, I'm not sure I understand what's happening, are you essentially "charging" the silicon-dioxide such that it retains its new charge? Is that new charge, then, responsible for attracting a charge in the conducting-channel, or is the conduction actually happening *through* the now-charged silicon-dioxide? Or something else entirely...? I really have no idea what I'm talking about.

Agree with @Stuart Longland, from a comment at: https://hackaday.io/project/16384-enhancement-to-depletion/log/47774-fresh-transistor-with-datalogging This is a great use of the scientific-method within a great "hack", well-deserving of project-number 2^14 :)

  Are you sure? yes | no

DeepSOIC wrote 10/22/2016 at 09:39 point

Thanks,

I think it's still an n-channel depletion mosfet, but I'm not totally sure about the terminology. But the conduction is n-channel, that's for sure. I couldn't have reversed the doping. And I'm quite sure the conduction is through silicon, not SiO2.

I have an opinion on what's going on, I hope to draw a picture eventually. But it is highly unlikely I'll be able to verify if I'm true.

  Are you sure? yes | no

esot.eric wrote 10/22/2016 at 12:07 point

Thanks for the insight about the sloped-conduction-channel.

Definitely interested in seeing your hypothesis/picture of how this thing's working.

  Are you sure? yes | no

DeepSOIC wrote 10/22/2016 at 10:15 point

The sloped conduction channel on your pic is likely to indicate the effect of resistive voltage drop across channel (due to current flowing through it). But it mayin theory also be built into the mosfet, e.g. by doping gradient, or by gate insulator thickness gradient...

  Are you sure? yes | no

Yann Guidon / YGDES wrote 10/22/2016 at 18:35 point

No, AFAIR, the gradient is due to other more mundane reasons, I forgot which...

  Are you sure? yes | no

Yann Guidon / YGDES wrote 10/21/2016 at 23:47 point

Would this work on a BS170/2N7000 ?

  Are you sure? yes | no

DeepSOIC wrote 10/22/2016 at 09:42 point

No idea. So far I have tried only one mosfet (two, actually, but same part numbers). Hopefully I'll try a few more mosfets. In particular, I am suspecting that it won't work on high voltage mosfets.

  Are you sure? yes | no

Yann Guidon / YGDES wrote 10/22/2016 at 18:37 point

So it should be safe with 2N7000 :-) Damnit, it's so hard finiding cheap BS250, and that could create very different and exciting (digital) circuit topologies !

  Are you sure? yes | no

RoGeorge wrote 10/21/2016 at 23:16 point

Very interesting. Is this transformation permanent?

Did you tried to use a variable voltage from the generator instead of the potentiometer? It would be interesting to see if the depletion mode will still be present after a couple of days of continuously varying the LED intensity. Maybe something like a triangle voltage, but with a frequency sweep, would be even more stressing.

Anyway, totally unexpected results so far, thanks for sharing!

  Are you sure? yes | no

DeepSOIC wrote 10/21/2016 at 23:35 point

Not sure about the permanence. So far it seems quite stable. It felt like it backed up a little bit during a few minutes/hour after the torture, but on the graph I can barely notice it.

With the very first mosfet, I even tried heating it up with soldering iron. The mosfet was near dead anyway.. It didn't feel like it has changed much then, but I didn't measure exatly. It was only proof-of-concept time

Hooking it up to a generator overnight sounds like an easy experiment to do!

  Are you sure? yes | no

helge wrote 10/22/2016 at 11:22 point

Congratulations to this cool project. Made me wonder if some less trustworthy manufactureres use the process you describe to tune bad threshold voltage values of MOSFETs with messy dielectric.

  Are you sure? yes | no

Yann Guidon / YGDES wrote 10/22/2016 at 20:04 point

@helge what an excellent question !

  Are you sure? yes | no

RoGeorge wrote 10/22/2016 at 22:37 point

Thank you very much for giving it a try. My bet is that the Ids might
make it to revert to its factory state. If the Vgs alone (with Ids=0)
will revert it, then it will be even more puzzling. 

Today I scavenged for 2 MOSFETs: one that it has a low Vgs(th), like yours has,
and the other with a higher Vgs(th). The first one is a PHP45N03LT and
the other is BUZ11A from ST. What I suspect is that only the one with a
low Vgs(th) in the datasheet can be altered, but for the moment I just
hope to be able to avoid any magic smoke.

:o)

  Are you sure? yes | no

helge wrote 10/22/2016 at 22:38 point

I wonder how that could be proven experimentally. Somewhere around 500-600°C the dopants will continue diffusing and messing everything up, altering the properties of the S and D implants and possibly the bulk contact will deteriorate. staying below that temperature regime it may be possible to liberate trapped charges (adding some moderate gate voltage may also help the cause), restoring baseline component behaviour. 

Something tells me it will be necessary to remove the package mold material to avoid mechanical stresses.

  Are you sure? yes | no

RoGeorge wrote 10/23/2016 at 05:48 point

IT WORKS, IT WORKS, I just replicate some of your results!

Well, in fact I did it by mistake :o), but at least now we know it's replicable on more then one MOSFET model.

Long story short, before starting to abuse the transistor, I wanted to trace Id versus Vgs. While I was doing just that with a BUZ11A, I ramped up by mistake the Vgs up to +32V. It was only for a couple of seconds, and with a positive gate voltage, not a negative one. Absolute maximum rating for Vgs of a BUZ11A is only +/-20V. All this time, Vds was set to 5V with a 3.2A current limit.

As a result, the threshold gate voltage was lowered from 3.84V to 1.57V.

  Are you sure? yes | no

DeepSOIC wrote 10/23/2016 at 10:40 point

@RoGeorge so, positive gate voltage lowered gate threshold voltage? That's unexpected, I thought it should increase... I should confirm it before publishing my explanation, it may be busting the explanation.

  Are you sure? yes | no

RoGeorge wrote 10/23/2016 at 16:17 point

@DeepSOIC, I'm very puzzled too. So far all my hypothesis were disproved. First, I
will try to reproduce once again some of the known results.
Then, continue with new experiment, but conducted more carefully, and in
a better controlled environment. The data will be available here: https://hackaday.io/project/16616

Now I need to go hunting for more MOSFETs.
:o)

  Are you sure? yes | no

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