anaGoL - Conway's Game of Life the analog way

A design for a non-microcontroller / non-digital logic Conway's Game of Life cellular automata simulator

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As I mentioned in this .stack post I'm looking into the possibility to design and build a Game of Life simulator using analog devices like summing amplifiers and window comparators.

Project Logs

1. PCB interconnects


Golang code for searching for optimal R2 & R3 resistor values in Roelh's schematic

go - 721.00 bytes - 02/18/2019 at 12:53



LTspice simulation for Roelh's first schematics

plain - 4.11 kB - 02/18/2019 at 12:38


  • Fully analog

    matseng02/22/2019 at 12:26 1 comment

    I've merged parts of the other designs into a new design using only analog components and not even having a BJT-flipflop, but rather a sample-and-hold to keep the state from just racing around the entire design uncontrollably.

    Running a simulation with a 4x4 matrix of these and adding the "Toad" pattern as the initial charges on the C3 sample&hold capacitor it runs just fine.

    I'll probably make a pcbs for this and add a few dozen of them to my next pcb order and see if they run in real life as well.

  • Low part count version

    roelh02/18/2019 at 18:18 2 comments

    I don't know if the rules forbid the use of a flipflop....  But the state of a cell is digital, isn't it ? So we use digital building blocks for that part.

    So a part of the previous design was replaced by a flipflop. 

    From a  practical point of view, it seems logical to place several cells on a single pcb, for instance 16. 

    Each cell needs 1/2 LM339 and 1/4 HC175, so for 16 cells this is 12 IC's. 

    The reset input (not in the diagram) of the HC175 can be used to reset the system to all zero. There should also be a possibility to pre-load a certain pattern, or several patterns (to be determined).

  • Proposal based on quad comparator

    roelh02/17/2019 at 09:46 18 comments

    The following circuit shows a possible way to do this. It uses a quad comparator similar to the LM339. Note that these can only sink current at their output, so they need a pull-up resistor. It also means that the outputs can be connected together to form a wired AND gate.

    I use an 8 volt power supply, in that case the voltage at the summing point will be (almost) equal to the number of surrounding active cells. Easy for measurements. But it will work with other voltages too. I here assume that the comparator outputs are almost equal to GND or VCC.

    The opamps A and B form a classic window comparator. The upper one compares to 3.5 V, the lower one compares to a voltage determined by R1, R2, R3. These resistors should be calculated such that:

    When the output of C is HIGH (cell dead), the voltage of the - terminal of B should be 2.5V, and

    When the output of C is LOW (cell alive), the voltage of the - terminal of B should be 1.5V,

    Comparator C holds the actual state of the cell. In each cycle, it gets a short negative-going reset pulse followed (or partially overlapped) by a positive going set pulse. The set pulse will only be effective if the set-signal is not shorted to ground by the window comparator. The C comparator has positive feedback so the state is remembered. The output drives a LED if the output is LOW, that indicates if the cell is alive. 

    The output of C is connected to the inverted input of D, that delivers a active-high signal for the neighbors. Note that there is a low-pass filter that keeps the output from changing while the pulses are applied. The output of the R1,R2,R3 circuit also has a capacitor with the same purpose.

    No tests or simulations were done yet, so it might be needed to do changes. It might also be possible to simplify the circuit. Note that the input summing resistors could be in a single resistor array. It should be checked that the comparators have sufficient input range.

  • 555 bending

    tophalfofabarn02/16/2019 at 04:22 6 comments

    So it turns out Conway's Game of Life is more complicated than I thought. I was under the impression it turns on a cell when there are sufficient neighbors, and turns it off when their are too few neighbors, which is exactly what a 555 timer does on an analog level. Easy peasy.

    But apparently it's more complicated than that, in which it turns off a cell if there are too many or too few neighbors, and turns it on if there is an exact amount of neighbors. Which is not what a 555 timer does. Not easily anyway.

    I had claimed this can be done with a single 555 timer, and I won't let a simple misunderstanding of the concept the entire project is based on slow me down. The 555 alone isn't really enough, so I threw in a zener diode to give me some nonlinearity to play with. (I have a few oddball computing projects in the works and have found out just how useful a tiny bit of nonlinearity can be). I made a sort of analog truth table:

    The biggest issue I see with this is that some comparisons are only made by 125mV. This should be enough, and can be dialed in by adjusting power supply voltage relative to the zener diode, but it's still a concern. I'll have to prototype something to know for sure whether it can work or not. 

    Here is a schematic that should achieve something close to that:

    Clocking is handled by holding the comparator inputs too far away from it's other input to ever trigger the flip flop. Setting works by forcing a comparator to trigger the flip flop.

    Another obvious problem, is that resistors have to get progressively larger in value for later stages to not affect earlier stages. I'll have to see what the CMOS version of the 555 timer requires. It shouldn't take too much current, so something on the order of 47k for the later stage resistors should be fine.

    I haven't yet done the math as to what the resistors should be, but it is simple to do from the first diagram. 

    This is of course just a design suggestion and not a final schematic, so input is welcome.

  • PCB interconnects

    matseng02/14/2019 at 17:11 0 comments

    Since I want to make it fully modular I need to have each PCB (pixel) both send its state to all eight neighbors as well as receive the neighbors states.

    I gave this problem statement, together with a strict rule of  "don't cross the streams (wires)", to my wife and she came up with something looking like this:

    Initial interconnect plan
    Initial interconnect plan

    Not bad at all actually.  But after looking at it for a while I realized it could be improved slightly by removing a redundant connection in the pass-troughs.

    Improved interconnect scheme
    Improved interconnect scheme

    This could also be slightly improved by switching the horizontal interconnects to reduce the trace length on the PCB a bit.

    I also need to add PWR and GND between all PCBs, but there's enough space for that at the left/right edge.

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tophalfofabarn wrote 02/16/2019 at 00:44 point

Happy to be on this project. I'll make a rough schematic tonight.

Also, Matseng, I'm pretty sure I know you from Dangerous Prototypes 7 years ago.

  Are you sure? yes | no

matseng wrote 02/16/2019 at 12:03 point

Ah yes... I was hanging at DP quite a lot a while back - but I really don't remember why I stopped being there

  Are you sure? yes | no

Ted Yapo wrote 02/15/2019 at 20:38 point

I looked into a discrete GoL implementation a couple of times. My first idea was a DTL register at each cell with a diode ROM for generating the next state from the neighboring bits. 512 diodes for each cell killed that idea pretty quick :-)

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Florian Festi wrote 02/15/2019 at 10:16 point

While those patterns look nice I don't think they solve the right problem:

All the outgoing arrows need to be connected on the board as they need to be fed from the component holding current state.

All the incoming arrows need to be connected to what ever adds them together. This may be build from multiple components so it may be OK to not have them meet at one place.

You will also need Clock going to all cells unless you can put the clock on the same line as VCC (buffering the current state with an cap while power is off).

If you want to build this from multiple identical boards:

The diagonals are a bad idea. It is difficult enough to put the grid together in two axis if you use fixed connectors. The diagonals basically force you to use cables.

The "Don't cross the streams" tactic does not take connectors into account. They create natural bridges you can put traces underneath. So the problem may be easier than you think

Not 100% sure if this really gives more degrees of freedom but I would look at connectors with two rows - like angled two row pin headers. This may make routing the traces even easier.

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matseng wrote 02/15/2019 at 11:38 point

Hmmm... Have I missed something in my planning?  (Except the GND, PWR and trigger common lines of course ^__^  )

As it is now each board have separate incoming connections from all its neighbors - and they will of course be summed together with 8 resistors on the PCB - or else it won't work.

Each board also have separate outgoing connections to all its eight neighbors. All the outgoing connections on the PCB will be connected to each other and to the "current state".

The "don't cross the streams" was not intended for internally at the PCB, but rather for the interconnects - I don't plan to use connectors there, but just soldered bare/unisolated wires.  To get all the boards aligned neatly with soldering I plan to use regular staples (used for stapling papers together), they have a reasonable size and are pre-bent.  The diagonals can then be soldered afterwards with hookup wires.

But maybe I should reconsider using 0.1" or 0.05" pinheaders instead, but the 0.1" females are really large and ugly, and the 0.05" probably are quite expensive compared to the 0.1".

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tophalfofabarn wrote 02/16/2019 at 00:56 point

Two trigger lines, actually, if the idea I have pans out. 

If you are soldering wires in for the bridges why not bridge with the summing resistors directly?

Also, if the plan is to make the configuration permanent instead of reconfigurable you could get away with only having power and clock lines run vertically, and then connect the bottom of each column horizontally with wire.

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matseng wrote 02/17/2019 at 09:01 point

@tophalfofabarn , using resistors as bridges probably is a good idea for both reducing the number of solder joints and also make the PCBs a bit smaller.  But I'm afraid that the array of PCBs will end up a bit crooked and askew if I'm using resistors that I bend by hand. Maybe I should enlist Bender Rodriguez to get it properly bent ;-)

Have the power bus and clock line just snake the way though the array a row at a time is probably a good ide.  My plan is to connect the edges to each other in order to get a "infinite" field so a glider or spaceship can just circle around forever - or else I'd need a *lot* of pixels to actually have anything visually pleasing for more than a few generations before it dies off or turns into a few blinkers.

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Dan Maloney wrote 02/14/2019 at 15:35 point

Glad this made it up from the stack. Looking forward to this one - keep us posted!

Now what about that mechanical GoL @Mike Szczys suggested...

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matseng wrote 02/14/2019 at 17:21 point

I think that this might end up bit on the back burner, but it's always good to have a place for it already made up whenever I make decide to really give it a go.

But I guess that I, as usual, will have a hard time to stop thinking about the electronics part of it, so very likely I will breadboard up one pixel to see if my half-baked idea of the electronics design will work at all or not.

My current focus should to be to finish up the Gold86 before my workload increases again and I won't have time to play with hobby stuffs anymore.

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Daren Schwenke wrote 02/14/2019 at 20:53 point

Good plan.  Just having that spot waiting for your thoughts when they happen makes all the difference.

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