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Building a 68030 computer in 5 stages

Based on Tiny030 design

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This project is to taking an existing 68030 PC board design and build it in stages. Each stage is functional so the construction can be checked. At stage 2 a bare minimal 68030 computer come to life with 3 chips. More capabilities are added in subsequent stages until a CP/M68K capable 68030 computer is realized in stage 5.

Here are Tiny030 design files:

Schematic, the schematic was created with the now obsolete WinDraft by IVEX.  The labels in green color are connections hooked up in pc board.  The labels in blue color need to be manually hook up.

Bill of Materials.

PC board gerber photoplots.  This board is layout with WinBoard by IVEX.  The pc board was manufactured by SeeedStudio.

The 5 stages of construction are:

1.  Assemble and programming the CPLD to blink a few LED,

2.  Minimal 68030 Computer

3. Basic 68030 with Serial port, RAM, and EPROM

4. 68030 with 16-meg DRAM,

5.  CP/M-68K ready 68030 computer.

stage4_68030_16M_DRAM.zip

EhBASIC running in 16 meg DRAM starting from 0x1000000

x-zip-compressed - 246.12 kB - 03/05/2019 at 14:46

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stage4_68030_test_16M_DRAM.zip

Test 16 meg DRAM added in stage 4

x-zip-compressed - 1.92 kB - 03/04/2019 at 16:20

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Stage4_CPLD.zip

Stage 4 CPLD, 16-meg DRAM added

x-zip-compressed - 70.34 kB - 03/02/2019 at 13:19

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Stage3_Tiny030_monitor.zip

Stage3_Tiny030_ROM_monitor

x-zip-compressed - 28.84 kB - 02/28/2019 at 13:36

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Stage3_Tiny030_memory_diag.zip

RAM diagnostic for Stage 3 Tiny030

x-zip-compressed - 4.44 kB - 02/28/2019 at 13:34

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View all 17 files

  • Stage 4 Software

    Plasmode03/04/2019 at 14:27 0 comments

    With the addition of 32-bit wide, 16-megabyte DRAM, Tiny030 is capable of running a varieties of application software quickly.  In this project we'll rerun the EhBASIC and memory diagnostic of Stage 3, add a new memory diagnostic for 16-meg DRAM, and do a benchmark of EhBASIC running in DRAM and compare that to EhBASIC running in 8-bit RAM.

    The existing ROM monitor runs fine in stage 4 hardware.  It now can access memory located from 0x1000000 to 0x1FFFFFF.

    I wrote a memory diagnostic to test 16 meg of DRAM


    EhBASIC is relocated to 0x1000000 and allocated 6 meg of RAM.  I measure the time it takes to run the ASCII mandelbrot at 27 seconds.  Compare that to 45 seconds running in 8-bit RAM of stage 3.  The improvement of 32-bit memory over the 8-bit memory is not as great as I would expected.  I believe one reason is because the 8-bit RAM is running at zero wait state while 32-bit memory has 2 wait states for the slower DRAM circuitry. 

  • Stage 4, Adding 16-meg DRAM

    Plasmode03/02/2019 at 13:29 0 comments

    Stage 4 hardware construction is manual intensive.  Installing U6-U8 (74HCT240) and socket for 16meg SIMM72 memory are straightforward, but there are many DRAM-related connections that are not hooked up in pc board.  Here is a list of connections that need to be manually wired:

    SignalCPLD pin68030 pin
    A2134A8
    A2235B7
    A2336A7
    A2437A6
    A2539B6
    SignalCPLD pinSIMM72 pin
    nRAS7644
    nCAS08140
    nCAS18043
    nCAS27941
    nCAS37742
    nSIMMWE7347
    SignalCPLD pinU7 (74HCT240) pin
    nENCASA751
    nENRASA7419
    SignalU7 (74HCT240) pinU7 (74HCT240) pin
    floating
    Input
    8Ground (10)
    floating
    input
    17Ground (10)

    The CPLD equations will need the DRAM controller and refresh logic added.  The refresh is CAS-before-RAS driven by a timer and logic that delays the assertion of 68030 DSACKx signals until CAS-before-RAS refresh cycle is completed.  This hidden refresh operation occurs once every 128 clock invisible to the 68030.  The DRAM controller is a digital delay tap clocked on rising as well as falling edge of clock.  Two wait states are needed to access the DRAM.  The design can be improved by using 74157 mulitiplexer to reduce the wait state to 1. 

    The 16-meg DRAM memory map is from 0x1000000-0x1FFFFFF.

  • Stage 3 Software

    Plasmode02/28/2019 at 13:29 0 comments

    Tiny030 at stage 3 is a fully functional computer.  I have developed a simple ROM monitor previously for 680x0 board so with small modification, it is suitable as Tiny030 ROM monitor.  As a monitor, it has the basic functions of display/modify memory, display/modify registers, load S-records, and execute program.  It communicates with the terminal program at 38400-N-8-1, no handshake.  It also perform basic I/O using TRAP15 calls compatible with EASy68K simulator, so a program can be simulated first with EASySIM and then load & execute in Tiny030 without modifications.  A 'he' command display the menu as follow:

    As a state-of-health indicator, the 7-segment LED displays the various state of the monitor software as it boots up and a rotating LED segments during idle state.  

    Since the address map of the RAM has changed since Stage 2, the memory diagnostic need to relocate to the new base address.  It is loaded & executed with the Tiny030 monitor.

    The memory diagnostic passes, so now I'm ready to load the EhBASIC which also need to be modified slightly to accommodate the different memory map between stage 2 and stage 3 hardware.  Once EhBASIC is loaded, I load up the mandelbrot program and run it.

    So Stage 3 Tiny030 has a functioning ROM monitor.  It passes memory diagnostic, and it can run real applications like EhBASIC.  We are ready to go to Stage 4.

  • Stage 3, 68030 with EPROM, RAM, and Dual UART

    Plasmode02/27/2019 at 16:22 0 comments

    The dual channel serial device, 68681 and EPROM are added in stage 3.  It would be very desirable to build on stage 2 serial bootstrap feature to test the hardware added in stage 3.  Alas, the board was not designed with that in mind and the amount of rewiring is too onerous.  The revised Tiny030 will have jumper configuration that preserves the serial bootstrap function as more devices are added.  This would enhance the board testing capability and help with development of the permanent EPROM bootstrap software.  With current hardware it is easiest to just dismantle the stage 2 hardware and add the 68681 and EPROM and get them working.  All the efforts in stage 2 are not lost, however.  We've found out that RAM/68030/CPLD are working correctly in stage 2, so if problems are encountered in stage 3, we can concentrate our efforts on the hardware that are added, i.e., EPROM and 68681.

    Picture below shows the stage 3 hardware configuration.  The EPROM and 68681 sockets are added to the pc board.  A zero-insertion-force socket is installed in EPROM's location to facilitate changing out EPROM.  A 3.6864MHz crystal is added as baud rate generator for 68681.  a 27K resistor is added across the crystal oscillator to bias it for oscillation.  I use this opportunity to install the voltage supervisor and change the CPU clock to 22MHz.

    The stage 3 CPLD equations are revised significantly.  The serial bootstrap function is no longer required; the EPROM is added to the memory map.  The chip select and interrupt signals of 68681 are added.  This is now the memory map of stage 3 Tiny030

    • EPROM 0x0-0x7FFFF
    • RAM 0x80000-0xFFFFF
    • 68681 0x100000-0x17FFFF
      •   Refer to 68681 data sheet for register mapping

    Stage 3 hardware is powered up and CPLD updated.  It is now ready for firmware and software.

  • Stage 2, Running Software on the minimal 68030 computer

    Plasmode02/25/2019 at 01:50 0 comments

    The minimal 68030 computer has 512K of RAM and a simple serial port.  Here is the memory map of stage 2 68030 computer:

    • RAM 0x0-0x7FFFF
    • Serial port transmit/receive: 0xFFFFF000
    • Serial port status 0xFFFFF001
      •   Bit 0 is TxEmpty, transmit buffer empty when high
      •   Bit 1 is RxRdy, receive data ready when high

    A very simple program to output 'hello world' on console looks like this:

        org 0
        dc.l $80000        ;define stack
        dc.l start
    start:
        lea signon,a0        ;point to sign on message
    chktxempty:
        btst.b #0,$FFFFF001    ;test for transmit buffer empty
        beq chktxempty
        move.b (a0)+,$FFFFF000    ;write next character to console
        bne chktxempty            ;until null terminator
        bra *                    ;spin forever here
    signon: dc.b $a,$d,'Hello World!!!!!',0
        end
    The assembler for this code is EASy68K.  The EASy68K tool chain has an utility, EASyBIN, that can convert S-record to binary format and fills the file to specified length which is 0xFF in this case.   This way the program will start running as soon as file loading is completed.

    OK, now that 68030 can receive a 255-byte program and execute it, let us write a 255-byte S-record loader.  This simple loader will load a S-record file and start program execution from 0x400 when loading is done.   To test this loader, I modified the above 'hello world' program so it starts from 0x400.  First load the S-record loader, and then load helloworld_400.


    That works, so I will now load and execute a memory diagnostic that checks the 1/2 meg RAM from 0x1000 to 0x7FFFF.  The program and stack reside below 0x1000 so that part of the memory can't be checked with the diagnostic.  First load the S-record loader, then load tstmem.s68


    That works well, now I'm ready to load a real application, Lee Davison's EhBASIC for 68000.  This program is available for download from EASy68K website.  The source code is modified slightly to accommodate the simple serial port.  Once EhBASIC is loaded and running, I will load a ASCII mandelbrot program and run it under EhBASIC.


    This collection of software demonstrate the stage 2 hardware is working properly and we are ready to move on to stage 3.

  • Stage 2, A minimal 68030 computer

    Plasmode02/21/2019 at 16:15 0 comments

    Once the CPLD is checked out and working, we are ready for stage 2.  Stage 2 is to assemble a bare minimum 68030 computer that contains 68030, RAM, CPLD and an oscillator.


    There are a number of manual wires need to be done at the back of the board:

    • Pull up nCIIN, nCBACK, nSTERM to pin 7 of SIP resistor pack R9
    • Connect Address 7 from pin 31 of CPLD to pin B13 of 68030
    • Cut the trace between pin A1 of 68030 to pin C3.  This isolates nBUSREQ from nBGACK of 68030
    • Connect pin 20 of CPLD to nBUSREQ (pin A1) of 68030
    • Connect pin 21 of CPLD to pin 83 (nAS) of CPLD
    • Connect pin 22 of CPLD to pin 84(R/W) of CPLD
    • Connect pin 54 of CPLD to test point T13
    • Connect pin 55 of CPLD to test point T14
    • Connect pin 56 of CPLD to test point T8
    • Connect pin 57 of CPLD to test point T24
    A prototype board with additional manual wires need to plug into the expansion headers, U11 to enable the serial bootstrap function

    Here is the board that's ready to power up.

    The USB-to-serial adapter connects to terminal emulation (I use TeraTerm) program at 115200-N-8-1.  Programmed in the CPLD is a simple serial port and DMA circuitry controlled by a state machine.  At power up the CPLD state machine generates a bus request to 68030, then the state machine takes control of the 68030 address and data bus and waits for serial data input.  Every data received is DMA to memory starting from location 0x0 until 255 bytes of data is received.  At that point the state machine relinquishes the bus and 68030 starts program execution from 0x0 like a normal power-on reset operation.  The small 255-byte program is typically a simple file loader that load more sophisticated application programs.  This is the mechanism by which the minimal 68030 computer can be loaded with diagnostic software to further test the board and to develop application software.  

    A reasonable question can be ask whether this stage is consider a "baby step" due to the many manual wires where mistakes can easily be made.  That's a good point for this particular version of pc board, but I also want to use this experience to develop a revised pc board where stage 2 can be done without too much manual wiring.

    This is the CPLD file for stage 2 68030 computer

  • First Stage, Assemble and Test the CPLD

    Plasmode02/21/2019 at 16:13 0 comments

    Start off with a blank Tiny030 pc board:

    The first stage is to assemble and test the CPLD by driving a few LEDs.  The CPLD is Altera EPM7128SLC84 hosted in a through-hole 84-pin PLCC socket.

    Add the 68681 40-pin socket because jumpers are needed to connect CPLD output to 7-segment display.  Populate the EPM7128SLC84 as shown and insert 4 jumpers from the 68681 socket as follow:

    • pin 12 to pin 35
    • pin 13 to pin 37
    • pin 14 to pin 9
    • pin 15 to pin 21

    This connect 4 currently unused CPLD outputs to 4 of the 7-segment display.  Also populate the oscillator.  Here is the Altera CPLD programming file.

View all 7 project logs

  • 1
    Building Instruction for Stage 3 of Tiny030

    There are lots of manual wires in Stage 2.  It is meant to help me designing a revised Tiny030 board.  If you are working with rev 0 pc board, you may want to do Stage 1 to check out CPLD functionalities, skip over Stage 2 and follow this Stage 3 Instruction.  Or if you are confident about the CPLD, you can start with this instruction and skips over stage 1 and stage 2.  Tiny030 pc board needs minor engineering change just for stage 3.  3 extra resistors are needed and 3 extra wires are needed.  The three pictures below show the component side of Tiny030 at stage 3, solder side, and lastly populated board.

    Picture below shows the location of two 22pF capacitors.  I do not have the leaded capacitors, so I substitute two SMT 22pF capacitors on the solder side of the pc board.

    Picture below show the engineering changes required for Stage 3 Tiny030


    The CPLD equations, ROM monitor, EhBASIC, and memory diagnostic described in stage 3 projects all work with this board.

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Discussions

Peabody1929 wrote 03/03/2019 at 00:58 point

I would like to run the 68030 with a minimum number of soldered wires.  Perhaps I could start  at Stage 3 and stay there.  How many wires must be added to run the board in Stage 3 only?   

  Are you sure? yes | no

Plasmode wrote 03/03/2019 at 01:48 point

If you want to go to stage 3 directly, you need 3 resistors and 3 extra wires.  You can skip stage 4 and go to stage 5 with 3 more wires.  Assuming you are using fast RAM like AS6C4008, you can run the RAM at zero wait up to 22MHz.  The performance with 8-bit fast RAM is roughly 1/3 of having 32-bit DRAM of stage 4.  I can build one up to verify what I said above tomorrow if you are interested in trying out stage 3.  --Bill

  Are you sure? yes | no

Peabody1929 wrote 03/03/2019 at 19:21 point

Hi  Bill,

That would be great!  I have a bare board on hand so it will be easy for me to duplicate the circuit.  THANK YOU!

  Are you sure? yes | no

Plasmode wrote 03/03/2019 at 02:31 point

Your comment also made me think about a different 68030 design.  The DRAM is fairly complicated circuit that requires a modest CPLD like EPM7128.  However, if we use 32-bit wide RAM (4xAS6C4008) and a 8-bit EPROM, a smaller EPM7064SLC44 can be used and the resulting 68030 still fit in 100mm x 100mm pc board.  It will also be faster than the DRAM version because static RAM can run with zero wait state, but the memory is limited to 2 megabytes with 4xAS6C4008 which is more than enough for CP/M, but too small for Linux.

  Are you sure? yes | no

Plasmode wrote 03/04/2019 at 05:49 point

I added an assembly instruction for stage 3 Tiny030 only.  It is in the 'Instructions' section of this project.   I've built the board and it is working properly.  I will add the CPLD equations and EPROM code to the instruction tomorrow.

  Are you sure? yes | no

Peabody1929 wrote 03/05/2019 at 00:26 point

I am almost finished building the board following your instructions for "Stage 3 Tiny030 only".  I need to get a socket for the 68030 tomorrow to complete the board.  Everything else is soldered on the board and ready to go.      

  Are you sure? yes | no

Plasmode wrote 03/05/2019 at 02:12 point

What kind of 68030 socket are you using.  I ask because I was generally not successful removing a large PGA package from its socket--the pc board is damaged in the process.  There are not enough room for zero-insertion socket, so I normally just solder the PGA directly on board.

  Are you sure? yes | no

Peabody1929 wrote 03/06/2019 at 00:54 point

A socket for the 68030 is an interesting problem!  It is a PGA socket specific to the device.  There are some extra pins in the central socket area.  This socket is  not available in normal distribution or the surplus venders in my area.  I thought I could get a socket with 4 rows of pins and remove some pins to get the 68030 pattern.  Unfortunately, that is not available either.  I did find the actual socket on eBay in China.  That may be the solution (in 4 weeks).

  Are you sure? yes | no

Alexander wrote 02/26/2019 at 07:56 point

This is such a cool project! I absolutely love building with older microprocessors, and combining in PLDs is the cherry on top. Will definitely be following this project to see where it goes!

Bravo!

  Are you sure? yes | no

Plasmode wrote 02/26/2019 at 13:24 point

Thank you!  I hope to learn from this exercise and design a 68030 pc board that's easy to assemble & test in baby steps.

  Are you sure? yes | no

Alexander wrote 03/05/2019 at 09:28 point

I am re-reading this again... this type of project gets me so excited to build stuff! I would LOVE to build a 286/386 board and run the very early versions of Linux on it. That'd be a blast! Quite a lot of work, though...

  Are you sure? yes | no

Plasmode wrote 02/23/2019 at 00:29 point

Build hardware in baby steps and test it at every step is a new idea for me.  I do think it is "hobbyist-friendly" approach and I should design with that in mind.  The Tiny030 was not designed for incremental assembly & test, but I'm revising it and will add features to make it so.

  Are you sure? yes | no

Plasmode wrote 02/22/2019 at 17:56 point

The CPLD is the glue logic.  Depends on which stage of development, it varies from a simple LED blinker at stage 1, to simple glue logic with serial bootstrap function in stage 2, back to simple decoder in stage 3, then it is DRAM controller, watchdog timer, memory decoder in stage 4 & 5.  The CPLD will be programmed several times as the assembly progress.  If something went wrong, the CPLD can also serve as hardware debug and simple logic analyzer.  This is why I want to check out the CPLD first.

  Are you sure? yes | no

Dan Maloney wrote 02/22/2019 at 21:04 point

Cool, I can see that. Pretty neat that the partially populated board can be tested with just a couple of jumper added in.

Interested in seeing this through the various phases. 

  Are you sure? yes | no

Dan Maloney wrote 02/22/2019 at 16:34 point

So many through-holes!

Help out a noob here - what's the CPLD do? Can't figure it out from the schematic.

  Are you sure? yes | no

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