YATAC78 - Yet Another TTL Archaic Computer (1978)
- Dual Processor CPU/GPU (Harvard Architecture).
- 32 MHz dot clock, 16 MHz memory clock, 8 MHz per processor (2-4 CPU MIPs)
- 256k ROM: 96k ALU, 64k native program, 64k relocatable code, 32k fonts.
- 128k RAM: 64k user, 43k display, 16k files, 5k buffers.
- 50+ ALU functions including multiply/divide and math functions.
- Bitmapped Graphics: Hi-res mode with 8 colors, 4 dithering patterns (320x240, 320x160 @ 75Hz, 320x256, 320x200 @ 60 Hz). Lo-res mode with 256 colors, double buffered (160x120, 160x96, 160x80 @ 75 Hz, 160x150, 160x120, 160x100 @ 60 Hz)
- Text Mode: 80 columns using code page 437, 8 colors FG/BG, 256 line buffer, up to 8 1/2 page smooth scroll. 8x8 glyph text (80x60, 80x48 @ 75 Hz, 80x75, 80x60 @ 60 Hz), 8x16 glyph text (80x30 @ 75 Hz, 80x36 @ 60 Hz)
- Audio: 2 melodic voices, 1 noise channel, 10 waveforms, ADSR, 9.6 kHz/8-bit DAC.
- PS2 Keyboard interface built in.
- RS232 Serial Port for host/client and network connectivity (9600 baud).
- Expansion Port: 7 addressable 8-bit registers in/out, 4 input flags, 1 flip-flop.
- Blinkenlights: 1
- Chip Count: 40 Total (34 TTL, 3 analog, 1 ROM, 1 RAM, and 1 PAL).
- Target PCB size: 8" x 5" (200 x 125mm) 4-layer board.
The system bus is clocked at 16MHz and a typical CPU instruction spans 4 clock cycles as follows:
- Fetch Instruction from ROM.
- Read data from source register or RAM.
- Execute ALU function using the ROM as lookup table.
- Write data to register and optionally accumulator and/or RAM.
The alternating use of both ROM and RAM allows a second processor to be added to the system. Both processors use a pipeline to cache data between the two address spaces. One processor handles serial communications and general computational tasks (CPU) while the other is dedicated to the display and audio (GPU).
The following sequence of diagrams demonstrates the multiplexing of the CPU (shown in blue) and GPU (shown in red). In this example the GPU is operating in text mode and the CPU is executing the sequence described in the numbered list above.
In the first cycle the GPU reads the ASCII code point of a character from the RAM and stores the result in the pipeline (gc). The CPU addresses the ROM using the Program Counter (PC) and Page Register (Pg) to fetch an instruction to the Instruction Register (I).
In the next cycle the context switches over and the CPU's X and Y registers are used to address the RAM and load the pipeline (cc). Meanwhile the gc, along with the Scan Register (S), is used to address the ROM and fetch a character bitmap line for the Glyph Register (G)
The GPU returns to the RAM where the H counter was moved to the next byte and loads the gc with text color values. The ROM is now configured as an ALU with a function specified in the instruction. The cc is combined with one half of the HL register and the result is stored in a register and Accumulator (A).
In the final cycle the value in A is written to the RAM. The font colors stored in gc are moved to the RAMDAC (C) and the bitmap loaded in to a shift register to start the next character render cycle.
Note: 8-bit ALU functions repeat the last two cycles to combine both halves of the HL register to form an 8-bit result.