YATAC78 - Yet Another TTL Archaic Computer (1978)
- Dual Processor CPU/GPU (Harvard Architecture).
- 32 MHz dot clock, 16 MHz machine clock, 8 MHz (4 MIPs) per processor.
- 256k ROM: 128k program, 60k ALU, 44k relocatable code, 24k fonts.
- 512k RAM: 8 banks of 64k, including 44k display.
- 55 ALU functions including multiply/divide
- Bitmapped Graphics 2 resolutions (75Hz refresh): 8 color hi-res mode at 320x240 (4 dithering patterns) or 256 color low-res mode at 160x120 (double buffered).
- Text Mode 640x480 native resolution (75Hz refresh). 4 fonts, 80x30 using 8x16 glyphs or 80x60 using 8x8 glyphs. 256 line buffer for 10-page smooth scroll.
- 8-bit PCM Audio with 20-18kHz bandwidth.
- PS2 Keyboard interface built in.
- RS232 Serial Port for host/client and network connectivity (up to 38400 baud).
- Parallel Port for expansion (up to 8 additional registers out, 1 register in).
- Chip Count 37 TTL, 3 analog, plus a single PAL, ROM, and RAM.
- Target PCB size single 8" x 5" (203 x 127mm) 4-layer board.
The system bus is clocked at 16MHz and a typical CPU instruction spans 4 clock cycles as follows:
- Load Instruction from ROM.
- Read data from source register or RAM.
- Perform an ALU function using the ROM as lookup table.
- Write data to accumulator, a register, and optionally to RAM.
The alternating use of both ROM and RAM allows a second processor to be added to the system. Both processors use dedicated pipelines to cache data between the alternate program and data address spaces. One processor handles serial communications and general computational tasks (CPU) while the other is dedicated to the display and audio (GPU).
The following sequence of diagrams demonstrates the multiplexing of the CPU (shown in blue) and GPU (shown in red). In this example the GPU is operating in text mode and the CPU is executing the sequence described in the numbered list above.
In the first cycle the GPU reads the ASCII code point of a character from the RAM and stores the result in the GPU Cache (gc). The CPU addresses the ROM using the Program Counter (PC) and Page Register (Pg) to load the Instruction Register (I).
In the next cycle the context switches over and the CPU X and Y registers are used to address the RAM and load the CPU Cache (cc). Meanwhile the gc, along with the Scan Counter (SC), is used to address the ROM and load a character bitmap line in to the Glyph Register (G)
The GPU returns to the RAM where the H counter was moved to the next byte and loads the gc with text color values. The ROM is now configured as an ALU with a function specified in the instruction. The cc is combined with one half of the HL register and the result is stored in the Accumulator (A).... Read more »