YATAC78 - Yet Another TTL Archaic Computer (1978 or 78k available RAM)
- Dual Processor CPU/GPU modified Harvard Architecture
- 13.5MHz machine clock, 6.75MHz per processor (up to 10 CPU MIPS)
- 256k ROM (128k for operating system), 128K RAM (78k for user programs)
- 75 ALU functions, including: BCD support, multiply/divide, square root, trigonometry
- 8-bit PCM Audio with 4 voices, 20-10 kHz bandwidth
- PS2 Keyboard interface built in
- RS232 Serial Port USB data transfer and internet connectivity (up to 38400 baud)
- Parallel Port for expansion (4 bits in, 8 bits out, 2 register strobes)
- Bitmapped Graphics 2 resolutions at 60Hz: 15 color hi-res mode at 320x256 or 256 color low-res mode at 160x128 (double buffered)
- Text Mode 640x400 native resolution at 75Hz. 4 fonts at 80x25 using 8x16 characters or 80x50 using 8x8 characters. 256 line buffer for smooth scrolling.
- Chip Count 44 TTL plus a single ROM, RAM, PAL, RS232 driver, analog switch, and op-amp.
- Target PCB size 2 stacked 18cm x 12cm 4-layer boards (25 chips per board)
The following gives a detailed overview of the system architecture and how the fast scheduling works. The system uses a 12.5 MHz clock and a typical instruction spans 4 clock cycles as follows:
- Load Instruction from ROM.
- Read data from source register or RAM.
- Perform an ALU function using the ROM as lookup table.
- Write data to register, accumulator, and optionally to RAM.
The alternating use of both ROM and RAM allows a second processor to be added to the system. Both processors use dedicated pipelines to cache data between the alternate program and data address spaces. One processor handles communication and general computational tasks (CPU) while the other is dedicated to the display and audio (GPU).
The following sequence of diagrams demonstrates the multiplexing of the CPU (shown in blue) and GPU (shown in red). In this example the GPU is operating in text mode and the CPU is executing the sequence described in the numbered list above.
In the first cycle the GPU reads the ASCII code point of a character from the RAM and stores the result in the GPU Cache (gc). The CPU addresses the ROM using the Program Counter (PC) and Page Register (Pg) to load the Instruction Register (I).
In the next cycle the context switches over and the CPU X and Y registers are used to address the RAM and load the CPU Cache (cc). Meanwhile the gc, along with the Scan Counter (SC), is used to address the ROM and load a character bitmap line in to the Character Register (C)
The GPU returns to the RAM where the H counter was moved to the next byte and loads the gc with text color values. The ROM is now configured as an ALU with a function specified in the instruction. The cc is combined with one half of the HL register and the result is stored in the Accumulator (A).
In the final cycle the value in A is written to the RAM. The font colors stored in gc are moved to the RAMDAC (P) and the bitmap loaded in to a shift register to start the next character render cycle.
Note: 8-bit ALU functions repeat the last two cycles to combine both halves of the HL register.