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GPU - part 1

A project log for YATAC78 - The WWW TTL Computer

Retro computer built from 1978-era TTL logic chips. Internet capable with built in web browser and server

Alastair HewittAlastair Hewitt 06/09/2019 at 01:210 Comments

The GPU consists of five 74F163 4-bit synchronous counters. The system is fully synchronous, so all counter receive the same 7.72 MHz clock regardless of the rate at which they ultimately count. The count is controlled by cascading the RCO/ENT (TC/CET) signals between the counters.

The first two counters form the Horizontal (H) register and connects to the lower half of the RAM address bus. The RCO signal from the second counter of the H register is used to reload the lower counter with a value of 12. This creates a count cycle that rolls over to 12 rather than 0 for a total count sequence of 244.

The H register is used to generate the horizontal timing signals and these are based on the VESA display timing formula (DTF). Generally this specifies a horizontal blanking (H-blank) period of 20% (48.8 cycles) and a horizontal sync (H-sync) period of 8% (19.52 cycles).

The H-sync is active when the upper 3 bits of the H register are low, so when the count is less than 32. Since the count starts at 12 the H-sync period lasts for 20 cycles, or 8.2% of the horizontal scan. The H-blank is active when the upper 2 bits of the H register are low and the next most significant 3 bits are not all high. This is the case when the count is less than 56 (64 - 8). Again, since the count starts at 12, this actually translates to 44 cycles. The RCO signal is also added the H-blank period, so the total blanking period is 45 cycles. This is slightly short to allow two cycles of overscan at the start and end of the blanking period to reach the required 49 cycles, or 20.08% of the horizontal scan.

The H-blank signal is used to inhibit the video DAC switch and effectively turn off the video signal for the 45 cycles of the blanking period. The video signal will be output for the other 199 cycles, where at least 4 of these cycles are still in the DTF blanking period. The nominal width of the display is 192, so the first 4 and last 3 cycles are considered to be overscan and would typically be blank pixels. However, the option exists to shift the screen slightly to the left or right to accommodate different monitors.

The RCO signal of the H register is used to enable the clock of the Scan Counter (SC). This is a single 4-bit counter that can count up to 16 horizontal lines. The outputs of the SC are combined, typically with AND gates, to create four additional RCO signals. These signals go high when the count reaches 1, 3, 7, or 15. The first of these signals is just the lower bit of scan counter and the last signal is the actual RCO of the counter.

These RCO signals allow the next counter to clock on every 2, 4, 8, or 16 horizontal lines. The specific signal depends on the video mode selected and will be described in details in the next log. The selected signal is used to enable the clock of the remaining two counters that form the Vertical (V) register. This register connects to the upper half of the RAM address bus allowing the combined H and V registers access to 61k of RAM (remember, the H register starts at 12).

The vertical count does not reset and will continue until it wraps around and returns to zero. The vertical register is accessible to the CPU though as one of it's 8 register targets. It is the responsibility of the CPU to reload the V register at the vertical scan rate of the video display. The CPU is also responsible for generating the vertical blank and sync signals by setting the appropriate bits on the extended (E) register.

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