Alastair HewittThe following gives an overview of the control signals shown in the schematic. There are a lot of them! The table below details the 20 registers/buffers/counters used in the YATAC. Each requires one or both of an output enable (~OE) and latch enable (~LE). Listed are the names, machine context, data source (SRC), destination (DST), and the control signals used by each register.
| Register Name | Context | SRC | DST | ~OE | ~LE | |
|---|---|---|---|---|---|---|
| Horizontal Counter | H | GPU | 0x38 | RAM A0-7 | qclk + H-blank | ~Hrco |
| Vertical Counter | V | GPU | ROM D0-7 | RAM A8-15 | qclk + H-blank | ~VLE |
| Scan Counter | SC | GPU | SC0-3 | ROM A8-11 | pclk + H-blank | - |
| GPU Cache | gc | GPU | RAM D0-7 | ROM A0-7 | pclk | qclk |
| Color Register | C | GPU | ROM A0-7 | VDAC | V-blank | ~CLE |
| Glyph Register | G | GPU | ROM D0-7 | SR D0-7 | - | pclk |
| X Index Register | X | CPU | ROM D0-7 | RAM A0-7 | pclk + ~XOE | ~XLE |
| X Index Read-back | X | CPU | RAM A0-7 | ROM D0-7 | ~XROE | - |
| Y Index Register | Y | CPU | ROM D0-7 | RAM A8-15 | pclk | ~YLE |
| Expansion Input | Ei | CPU | serial port | RAM D0-3 | ~EOE | - |
| CPU Cache | cc | CPU | RAM D0-7 | ROM A0-7 | ~ALUE | pclk |
| ALU Function | fn | CPU | I0-2, I6 | ROM A12-15 | ~FNOE | - |
| Accumulator | A | CPU | ROM D0-7 | RAM D0-7 | ~AOE | ~ALE |
| HL Register | HL | CPU | ROM D0-7 | ROM A8-11 | - | ~HLLE |
| Program Counter | PC | CPU | ROM D0-7 | ROM A0-7 | A17 | ~PCLE |
| Page Register | Pg | CPU | ROM D0-7 | ROM A8-15 | ~PgOE | ~PgLE |
| Expansion Output | Eo | CPU | ROM D0-7 | serial ports | - | ~EOE |
| Instruction Register | I | CPU | ROM D0-7 | decode | - | ~ILE |
| Expansion X Register | EX | CPU | ROM D0-7 | parallel port | - | ~EXLE |
| Expansion Y Register | EY | CPU | ROM D0-7 | parallel port | - | ~EYLE |
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