First Board soldered

A project log for FBus: Open FPGA Realtime Bus

Defining and implementing a bus protocol that is built around low-cost FPGAs to enable modular and affordable control and DAQ systems.

flowflow 04/08/2019 at 22:340 Comments

The first Board is soldered :-). On this board I did not populate the DDR2 memory or the associated power supply to reduce the total points of possible failure.

As a first test I flashed a bootloader on the SAMD10 and it worked :-). In the next days I will implement bitstream loading for the Lattice ECP5.