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Pipeline segments description

A project log for FPGA Game Console

This is my graduation project for B.Sc. in Electrical and Electricity Engineering.

StanislavStanislav 04/16/2019 at 05:330 Comments

First update, I already finished hardware implementation of CPU in Logisim simulator. 

We have there:

IF segment for instructions. ROM with 16 bit address width. We will not need all of the memory, also Cyclone II don't have such a big amount of memory for implement 64kB. Logisim will create a kind of look-up table in VHDL, for every address value we will get it's data value. I started to write game code in pseudo Assembly and at the moment I have about 150 lines, every command takes 4 bytes. I guess all game will not exceed over 4kb.

ID segment for register fetching. Here we will navigate all registers to their destination. We have 8 registers: AX, BX, CX, DX, PSW, XP, YP, SP.

First four is for logic and arithmetic operations. PSW is flags register(zero, carry, sign, parity).

XP, YP - registers for coordinates on the screen.

SP - Stack Pointer.

BC segment is to simplify branch control of the pipeline. The segment calculates branch condition and also new address value to jump in one clock. If branch is take a place then pervious stage is wiped. Near to this segment we have Branch control box for buffer control signal and new address.

MEM segment - Read/Write memory, 1 byte each time. Also Push and pop commands, we have MUX for switch between memory address and stack pointer registers. Also we will use Dual-port RAM, that means CPU and PPU can access the RAM together and we will not need to control timings.

EXE segment for logic and arithmetic operations.

WB for navigation data flow.

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