This is how it could be implemented (drawn in my Circuits.CC online editor):

As you can see it writes data to register at the end of BDOUT=0 and BSYNC=0 (Q-bus write cycle) when BBS7=0 (it means A15=A14=A13=1) and A11=A12=1 (so technically speaking it will respond on any address from 0xF800 to 0xFFFE, but for future compatibility we are saying that address must be 0xFF00). We will use inverted outputs (REG0...REG15) to fix our inverted data bus and straight outputs will go to 16 LEDs for indication. Also BINIT signal will clean the register on boot (but because we use inverted outputs we will get value 0xFFFF). And finally we have signal !RDEN (read enabled) to connect buffer to databus when CPU reads (BDIN=0 and BSYNC=0 that is Q-bus read cycle) from address 0xFF00 (actual buffer schematics will be added later).

TO BE CONTINUED