Our last episode covering the FPGA capabilities deserved a quick followup to shed some light into what's coming next in the hopefully near future:
Icestudio GUI getting huge improvements
Hardcore developers will handle any problem with any fpga using any language to get things done. For the rest of us, its neat when the user interface is friendlier than a bunch of HDL files.
Several updates happened to the icestudio.io project, with massive speedups showing up in the nighties. This speedup is allowing to work with really large FPGA projects.
Lets see a couple of examples from the developers mailing list. The list is in Spanish so its good to unearth that huge effort and show a bit what's going on there.
Z80 processor + peripherals
This is not just a drawing, this is the actual view in the ice40 Icestudio editor. You can actually drop a Z80 CPU, UART, RAM, Bootloader and GPIO blocks into icestudio. Verify, synthesise, and upload to the target is a breeze.
Yes, this is really happening, in a fully open source FPGA toolchain! It was about time, after all we were promised 2019 was the year of the FPGAs!
RISC-V + peripherals
Z80 not cool enough for you?
There is a RISC-V core available and passing tests on the ice40 devices, together with a UART, RAM and external flash management ready for you to discover and try out. Kudos to Obijuan for sharing this demo!
The coolest bit of this is that you can use gcc to compile C code that runs in this softcore, and the code example is awesome, directly accessing your custom "peripheral" from the address map:
You can see it doesn't need any fancy include, and when you consider it was you who built the whole cpu logic, its just mindblowing.
An actual motor control application
Alright alright, that toolchain is very cool, but how does it benefit my motor control application?
The main point of Axiom having an FPGA is to digitize earlier the analog signals.
These digitizers are footprint compatible with the AMC1302 iso-amps currently installed which are actually delta sigma converters but they convert the signal back to analog domain. By swapping them you can digitize right at the High Voltage domain, and it stays digital until it reaches the microcontroller for field oriented control calculations.
What's the benefit?
First you can ditch all these analog signal processing components, they are a big chunk of the BOM and pcb area!
All these components can be removed if Axiom goes digital
Not only they add cost to the BOM, but most importantly they add ageing, temperature and tolerance drifts; supply rail variations and EMI will creep up into the measurements, and in these critical applications, every parameter drift has to be studied to perform the design assurance our big customers are already requesting.
For example if the signal chain has x2 opamps, x7 1% resistors and x4 10% capacitors, you can calculate the worst case scenario in which the signal chain will have 10% of error. That's likely unacceptable, so you run a Monte Carlo analysis that tells you that 99.8% of the boards will meet <5% tolerance, but now you need to test every board under various conditions looking for the 0.2% that needs to be scrapped or somehow tuned.
Enter the digital signal path
Everything we did in the analog domain we can do it in its digital counterpart. Drop a delta sigma demodulator block, a sinc filter, a decimation filter and you are ready to go. This takes only a few hundred logic blocks.
This signal chain and its benefits are well documented in this article by Analog Devices
For the hardware overcurrent/overvoltage comparators there are methods that will detect the incoming fault within 4 us with a few logic gates. That's usually done by branching off another filter from the 1-bit stream but with quicker response time. So for example if you get seven "1" in a row that can be enough to indicate a fault condition and shut down the drive, and for safety standards this count as "hardware-based protection".
Repeat the signal chain 7 times (x3 currents and x4 voltages), send the data over high speed SPI and you're done. Most current sensors have analog outputs, but we already developed a current sensor with delta sigma output that is actually lower cost than its HALL counterparts.
You can sync the sampling exactly on the center of the PMW activity like the MCU does, and by tweaking a bit the OSR you can place notch exactly at your pwm freq, removing a lot of noise from your signal.
Analog's article goes in depth explaining how the impulse response attenuates the weight of the samples taken at the switching times.
Noise near switching events weigh less after going through the impulse response of the sinc3 filter
We have run our own math to produce the correct combination of modulation frequency, oversampling and decimation to locate the notches in the digital filter chain at exactly 18kHz which is our target switching frequency. Need a different frequency? Tune a few parameters and you're ready to go.
The response plot you get is nothing short of amazing:
Not only you get a notch in your 18kHz, but all the harmonics in the green plot get notched-out
Basic tests and results were promising - no one got hurt! -
Yellow channel: Delta Sigma output of a 100Hz sine
Sinc3 filter and decimation was developed in verilog, ready to be replicated in the system:
Icestudio makes testbenching easier, and results are shown in gtkwave
Testbench of Axiom delta sigma demodulator+sinc3 using real data from a sensor
If we really go down this path we can drop in the 144 pin STM32F4 that can expose the full bus on the pins and gain instant access to the data as a directly memory-mapped area instead of SPI.
So this is a peek into the future of Axiom, the groundwork is ready but its a steep development effort that requires quite a bit of funding, and right now we are really busy with documentation for the future users as the current embodiment is already earth-shattering!
Until then, have fun!