Language and target architecture

A project log for High level turbo FPGA development system

This project is about developing an easy-to-use high-level hardware development tool, and an FPGA board to use it on.

will.stevenswill.stevens 04/13/2019 at 19:200 Comments

The starting point for this project will be a compiler for a subset of the Handel-C language. I want to target Lattice iCE40 FPGAs, because the bitstream for these devices has been reverse engineered, and open source place and route tools are available. (See project IceStorm).

This compiler is based on the same research into hardware compilation that Handel-C was based on. One of the key papers can be found here: Compiling occam into FPGAs

Initially my Handel-C subset compiler will be modified to produce verilog output (it was originally written to produce VHDL suitable for Atmel AT40K FPGAs), which can be fed into the IceStorm tools. Later, the compiler will produce a netlist, and I’ll write my own tools to map and place-and-route for the iCE40 architecture.