Tomodachi X2

A modern retro system, compatible with the C64 and others.

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As the number of still working Commodore 64, Sinclair and Atari systems dwindle, there is still a lot of demand for such systems, both by those who used such systems back in the 80s and 90s and those who have discovered such systems later on.

The Tomodachi ('friends' in Japanese) X2 project intents to capture all that makes such retro systems so attractive to use along with all of the nostalgic bits, while adding a dose of modern electronics that nevertheless should not get in the way of enjoying all the good that 8 and 16-bit systems had to offer.

Along with full hardware 6502 and Z80 compatibility and an integrated C64/128 and other modes, the Tomodachi X2 project can also be used as its own multi-processor, multi-architecture system, with many interfaces including PS/2, Ethernet, serial & parallel, 3.5" floppy drive support, a Yamaha OPL3 synthesizer chip, high-resolution graphics and much more.

The project's PCB is being designed in KiCad, using a Mini-ITX-compatible layout to allow prototypes to use existing enclosures. The final product may very well use a different form factor. Regardless, the specifications at this point are:

  • Mini-ITX form factor
  • W65C816 MPU (x2)
  • eZ80-190 MPU (x2)
  • 256+ MB of DDR3 SDRAM
  • "Alice" chipset.
  • Yamaha OPL3 synthesizer
  • Commodore 8580 SID (x2)
  • Commodore 6581 SID (x2)
  • 100 Mbit Ethernet
  • SD card reader
  • LPT port
  • COM port (x2)
  • DisplayPort output
  • DVI output (VGA compatible)
  • Stereo audio out
  • Single 3.5" floppy drive

Current status:

  • Developing the "Alice" chipset using a Lattice ECP5-based development board.
  • Sampling a number of (Microchip) Super-I/O ICs (SCH5027, SCH5627) that are 3.3V & LPC compliant.
  • Planning expansion boards for the MPUs and external peripherals for development after "Alice" matures sufficiently.
  • Brainstorming on details, such as which ways one should be able to select the system mode.

  • Let the development commence

    Maya Posch06/25/2019 at 16:03 0 comments

    Over the past weeks/months/too much time, I have been primarily occupying myself with the details of the "Alice" chipset, as this is the magic sauce that will make Tomodachi X2 either awesome or not so cool. Details such as how to switch between system modes, how to make everything flexible enough that one isn't limited to just a handful of options, and maybe most importantly of all, what 'native Tomodachi mode' is all about.

    While brainstorming about this both by myself and with some friends, it quickly became obvious that while one could totally use one or more of the hardware CPUs on the board for native mode, it would be easier and much more powerful to use a more modern architecture. That's when picking a RISC-V core came into the picture.

    These cores are nice and small, with some taking up only a few thousand LEs on an FPGA like the ECP5. Meanwhile they are efficient (depending on the core in question, of course) and very flexible due to the RISC-V architecture. This led to us poking at a number of cores, including f32c, Rocket and a funky one called Potato. Depending on which of these are the least painful to use, and with a strong preference for VHDL will ultimately decide which one will be featured on the first functional TX2 prototype.

    Best thing of course is that since they all use the RISC-V ISA, switching cores later on is totally cool, as the software will still run.

    As for the architecture of the chipset itself, it'll likely end up looking somewhat like this:

    Using a crossbar switch fabric to tie relevant elements together, and likely splitting mode-specific peripherals (such as the C64 PLA, ROMs and CIA chips) into their own modules should provide maximum flexibility. Meanwhile the SDRAM controller (DDR3 or otherwise) would be designed to accommodate different modes, such as 16- or 24-bit addressing, even allowing each MPU to have its own dedicated block of RAM, up to 64 kB or 16 MB.

    As far as mode selection goes, one might be reminded of the C128, where one had to remember in which mode one was, followed by performing the required ritual steps to boot into the other mode: C128 manual.

    Here a thought is to either boot into native mode, and execute a command there that will perform the switch, or have physical switches (hooked up to the bootloader in the FPGA) that can set the desired mode before one powers up the system. Perhaps a tad Altair 8800-ish, but could be useful if one intends to use the system in a specific mode for an extended period of time.

  • Settling on a first prototype design

    Maya Posch05/10/2019 at 09:27 0 comments

    The Tomodachi project isn't a new one. It's something which I have toyed with in some form or another probably since the 1990s. What is new is that for the first time I have decided to put my love for those old home computers and modern technology together to make a system that is practical to make (now and during the coming years/decades). It should also cover all of the points that made systems back then so much fun to use, while not shying away from new technologies that enhance the experience instead of taking away from it.

    After months of brainstorming, the design that I came up with is basically the following:

    I have had people comment on this diagram with 'it's basically a Commodore 128!', which I think is fair enough. It has the same 6502 compatibility (in the form of the 65C816) and CP/M-via-Z80 compatibility as the C128, though it ups the game by having the 16-bit successor to the 6502, as well as the modern, pipelined version of the Z80.

    Also, it has two of each MPU, with the chipset providing access to the full range of DRAM, meaning 16 MB of RAM per 65C816 and eZ80-190 and DMA possible between these RAM segments as well as peripherals. Because there should be peripherals. From a floppy drive (obviously), to Ethernet (100 Mbit at least), to a range of synthesizer chips (Yamaha OPL2, stereo SIDs), as well as LPT (parallel) and COM (serial) ports.

    Video isn't drawn explicitly into this diagram, but will be integrated into the chipset, with both VIC-II compatibility as well as its own, 1080p (or better) capable video adapter, outputting video likely via DVI-I (digital & analog output) and DisplayPort.

    At this stage a Mini-ITX compatible board layout is being targeted, with the schematic and board layout gradually being finished for the first prototype board. All of this is done in KiCad, naturally. For the chipset an FPGA will be used, with the Lattice ECP5 (without SERDES) being a likely target. Much like the PLA in the C64, it's this chipset that will be the 'magic sauce' that makes the whole system work.

    After initial prototyping, fun details such as which shell to use will pop up. Clearly, the system should boot from ROM like the C128 and C64 for that 'instant on' experience. Whether one would use a BASIC shell of some type, boot into a DOS, or use a Forth shell (why not?) is all still up in the air.

    My hope is that others will feel interested enough in this project to pitch in, even if it is just with some ideas and sketches on the back of envelopes, scanned in and faxed to me. It's going to be fun, I'm sure :)

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AVR wrote 06/25/2019 at 17:24 point

love the idea of this and looking forward to your progress! Might be interesting to me as a synth platform since you are including the SIDs and the yamaha chipset all in one board. 

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Maya Posch wrote 06/26/2019 at 14:41 point

Thank you for your interest! :)

That's indeed another interesting thing that TX2 could be used for, yes. Depending on user feedback, other chips might also be included. So far I settled on the most popular chips, but it's by no means the final list.

The OPL4 is another one which seems interesting, as well as other chips from that era.

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AVR wrote 06/29/2019 at 02:49 point

I think you got a great set of chips already one or two wouldn't hurt lol, maybe an AVR with some sort of wacky open source soundcard like firmware IDK, just to add yet another layer to it all lol. 

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