Running short fragment of program - but needs a lot of fixing!

A project log for Let's experiment: NEC V20 + FPGA

What happens when you connect a NEC V20 to an FPGA? Let's find out!

NYH-workshopNYH-workshop 05/26/2019 at 14:420 Comments

I have squeezed some simple instructions into a 16-byte ROM that writes 0x04 into the I/O address 0x00, and repeats (

MOV AL, 04
OUT 00, AL

This is then converted into machine code  (, and I write this in the *.mem file that the Quartus 2 can deploy into the array (

module storageReadOnly(output [7:0] data, input [19:0] addr, input RD);

reg [7:0] memory16bytes [16:0]; 

initial $readmemh("rom_image.mem", memory16bytes);

assign data = memory16bytes[addr & 20'h0000f];


The "rom_image.mem":

B0 04 E6 00 EB FA

 And here it runs:

However, the decoding part isn't the most straightforward thing to write in Verilog. I'm not even sure if my version of decoding could work:

always @(negedge ASTB) begin
	if(A0_19 >= 20'hffff0 && A0_19 <= 20'hfffff)
		CS_IO_1 <= 1'b1;
		CS_IO_1 <= 1'b0;

 This CS_IO_1 is a temporary chip-select to select an I/O address which I will connect these to the LEDs later to verify the operation. I'll expand on the V20 writing to the FPGA after this.