I’ve written about the inverter’s transformer design and current management scheme in other logs so I figured I round it off with one on the gate drive and transistors.
A big goal in this design was a reduced layout in terms of both physical space and electrical distance. Going vertical seemed like a sensible way to do this. It has the added advantage of placing the low power & logic components on a separate board thereby reducing thermal stress.
This part of the design has worked well. The 100mil right-angle mounting pins aren't the best for density but they do provide good support. A separate board allows for potential reuse in other designs and for upgrades without obsoleting the base design. The main (power) board can also use heavier copper for the high currents without creating problems for the close traces required of the logic components.
International Rectifier’s IRS21864, monolithic, half-bridge gate driver is used. It’s actually a high voltage model and is used on the sine section as well. It’s used here to reduce the parts mix and because it otherwise supports a 4A gate drive source/sink and is single supply. I also selected it because of prior experience with other parts from this family. They are very durable, have good noise immunity, and tolerate ridiculous amounts of ground bounce. Ground bounce refers to refer to the phenomenon of Vs and COM below ground. Both are due to high di/dt, transformer flyback, and the parasitic inductances (e.g. transistor leads, PCB traces, etc.).
Vs below ground refers to the gate driver’s Vs pin that is connected to the center leg of the half-bridge. During turn-off of the low side the transformer’s primary reverses polarity by flyback action. Vs will move below ground by the MOSFET body diodes’s Vf plus series voltages induced by the parasitics and the di/dt. COM below ground refers to the gate driver’s COM pin that is connected to the source of the low-side MOSFET. This is the reverse of Vs: during turn-off the parasitic inductances in series with the transistor and the star ground reverse polarity and induce a flyback voltage based on the di/dt.
It doesn’t take much parasitic inductance to wreak havoc. Given that the instantaneous voltage across an inductor is:
L * (di / dt) = V (1)
Conservatively assuming that the total parasitic inductance of the source-ground is 7nH (a standard hight mounted TO-220 could have this much), using the Iin_max (current in, max) value for this design of 45A, and a turn-off / fall time of 84nS (ref. ‘mosfet-inv’ tab of design workbook):
7nH * (45 / 84nS) = 3.75V (2)
I haven’t done formal measurements on the design but I’m sure that they are higher than this and is a key reason why I didn’t use low-side current sensing in this design. IR guarantees the gate driver operational with COM up to 5V below ground. Beyond this damage occurs. This is due to the internal diode structures.
The ground margin on Vs is higher and depends on the gate driver’s Vcc. In this design the margin is 13v:
Max Vcc = 20V
- Design Vcc = 12V
Vcc Margin = 8V
+ Ground Margin = 5V
Total Margin = 13V
The high-side driver will latch-up when Vs exceeds 5V below ground but won’t incur damage until the total margin is exceeded. The TS350 is likely exceeding 5V but it isn’t a problem since the high-side transistor is off.
Fortunately the design didn’t require special compensation to protect from these conditions and resulted in a simple design. The gate drive resistors are sized to minimize switching times within the source/sink limits of the gate drivers. Current limit resistors in the bootstrap charge circuit protect the diodes. Generous bulk capacitance is provided between Vcc and COM since this is the current source for both bootstrap capacitor charge and low-side gate drive. Note the bulky 2220 packages - not required but a symptom of the MLCC shortage.
The PCB layout is optimized to minimize the gate drive current loops. Although the controller gate traces meet criteria as a lumped system the ‘B’ traces include a delay to match the ‘A’ side. Ground pins are interleaved with high speed signals to minimize crosstalk. Both internal layers are used as ground planes.
TI’s CSD19535KCS is used to switch the inverter bridge. It was selected for its low Rds(on), high switching speed, relatively low gate charge (Qg), and high current handling capability. Like the gate drivers, this transistor is also used in the SSR. So far it has proven to be a durable performer - no failures in semi-destructive (high temps, shorts) testing yet.
As mentioned in the current management log these are mounted at minimum height to reduce their parasitic inductance. RC snubbers are included as optional in the design. Evaluation showed that they did not materially reduce transistor heat dissipation or switching rings. Rather they increased losses thru their own dissipation.