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MockA65xx - Universal 6502/85xx CPU replacement

Project to reverse-engineer and create edge-level exact replacements for major MOS6502-derivatives and also other MOS/CSG chips!

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Project to reverse-engineer and create edge-level exact replacements for MOS6502-derivatives and also other MOS/CSG chips.

So far the following CPUs are planned or already implemented:

6502
6508
6509
6510T
6510 (aka 8500)
8501
8502

The actual 6502-derivative to be replaced can be selected via four solder bridges on the
bottom layer of the PCB. That means: One MockA65xx fits it all!

Inspired by the Visual6502 and Monster6502 project and my previous work on reverse-engineering the digital part of the famous 6581/SID chip I decided to create an edge-level exact replacement of the MOS6502 to replace its major derivatives. In order to exactly mimic their behavior I chose to dig deep into the schematics, die shots etc. One by-product is the MockA65xx hardware that is quite similar to the now hard-to-find GoDIL40 module - but smaller and cheaper.

MockA65xx_Pins.pdf

Overview of the derivatives planned initially... might be obsolete now! :-)

Adobe Portable Document Format - 24.19 kB - 05/17/2019 at 08:14

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  • Another picture for my man cave!

    androSID07/02/2020 at 16:05 2 comments

    The last few months I vectorized the CSG8501R4 which serves as test bench for my HDL code generator. This monkey work took me several months (not full time of course)... but here's the result printed on brushed alloy for my man cave:

    Astonishingly my wife wasn't too disgusted!
    She even suggested to hang this picture in one of "our" rooms... STRIKE! :-D

  • New prototypes on the way!

    androSID02/25/2020 at 14:30 1 comment

    Finally my buddy Thomas found the time to work on the layout for the next prototype :


    Though it's not obvious this was REALLY hard work. The 4-layer PCB is very tight and by example moving the DEBUG port inwards took several days...

  • Back on track after repairing one of the prototypes!

    androSID12/25/2019 at 10:39 1 comment

    Today I finally found the time to re-solder my main prototype which ceased function some days ago. That means I removed the old MAX10 (10M02) device and placed a new bigger one (in terms of logic cells) on it. Luckily it worked immediately after taking it out of the vapor-pahse oven! Manually placing a 169 pin BGA on a PCB isn't that hard it seems...

    ... now I can get back to work. While my 8501 logic works reliably now there are still some minor timing issues left in the 6502 core. But nothing serious! Happy X-Mas to all of you!

    PS: It seems the prototypes were soldered with hot air only which wasn't that "healthy" for the FPGAs.

  • Sometimes SMT/SMD just suckz...

    androSID12/02/2019 at 12:44 0 comments

    Last week I tried to get my 8501 core (very slightly extended 6502 core)
    running on my MockA65xx - but without success! Bad luck!

    In order to nail down the problem I decided to use my HDL code on Jim Brain's Fake7501 - (7501/8501 to 6502 Adapter) together with an original MOS6502A in order to check if my 6502 core or the 8501 GATE IN logic is wrong... In the end it turned out that neither the CPU nor the GATE IN was wrong but that at least one of the pins of the damn prototype(s!). All four prototypes suffer the same problem:
    Missing solderpaste on some of the contacts. Unfortunately a few of the contacts are located below the FPGA (BGA case)... and that really suckz as I currently have no possibility to rework them. I was just lucky that the board I picked 1st and mainly used was just the best with fewer errors... However one good thing: At least I could help a friend of mine now to further improve his reworked C16 mainboard (64kB, better video signal routing, better PSU etc.) to work with a cheap 6502A instead of the 8501 which is far more expensive. For those of you who understand german: Rework of C16 Board PS: And of course I now know that my GATE IN (the little H/W extension that turns a 6502 to a 8501) logic is correct.

  • Some artwork for my office...

    androSID11/11/2019 at 21:07 0 comments

    I hope you don't mind me spamming my own blog as this one is only slightly related to the project:

    A little artwork/picture for my office! Doesn't it look cool??? At least for a nerd like me it does!

    PS: It's the die of the 6510 (or more exact it's successor 8500).

  • New protoype working!

    androSID11/11/2019 at 20:39 0 comments

    Having enjoyed (no... not really) a quite long pause from this project I got back to it a few days ago.

    Doing a major revamp of the Top Level Interface I finally made all external timings (Setup, hold times etc.) adjustable and made the whole thing 100% edge level exact to the "real thing" now. I'm glad that the new hardware and new FPGA code are working... but see yourself:

    The next


    The next steps will be 6510 (once again to be able to run the Lorenz Test Suite) and the 8501 as this one seems to be needed... maybe the only one of the bunch!? LOL

  • Work resumed...

    androSID09/27/2019 at 14:00 0 comments

    Over summer vacation I lost a little bit of drive (i.e. motivation) but I'm back now! :-)

    While I reverse engineered the GATE IN circuitry a while ago I was not happy with the

    pictures of the die... so I had re-do them just for the sake of doing it:

    MOS8501R4 metal vs. poly layer

  • Even MOS/CSG was re-using layouts!

    androSID07/09/2019 at 15:06 0 comments

    When starting the project I actually used die shots which were much worse

    than the ones I use now (for other projects):

    MOS8500R4 (aka 6510) vs. MOS8501R4

    Although picture quality is quite embarrassing I could get use them because of

    their similarity. That means: MOS/CSG really re-used chip masks which can

    clearly be seen here.

  • That's what happens when I cannot sleep! :-\

    androSID07/05/2019 at 15:04 0 comments

    Sometimes insomnia is good... some results from yesterday night:

    Metal <-> Poly layer of MOS8360R2 (aka TED PAL+NTSC).

    At least it's more than good enough for conversion to netlist.

  • Making progress... slowly! :-)

    androSID07/02/2019 at 12:38 0 comments

    I was lazy busy in the last weeks... mainly stitching upcoming die shots
    which I had to verify/check in time for errors for future projects. (Hint hint: Stay tuned!).

    Anyway I redid (stitching) the MOS6509R7 just for fun:

    Metal <-> Poly layer of MOS6509R7

    Well... to be honest:

    Actually there was no point doing the MOS6509R7 again as I already
    reversed the relevant parts. In fact I did it not for fun but in order to improve
    my workflow and to speed up development by using the vectorized die shot
    directly for simulation.

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Starhawk wrote 06/15/2020 at 17:35 point

I see the configuration-jumper thing ;) very cool, very clever. I like :D need something for completely custom stuff, tho, and a configurator GUI or something... like, a jumper for "other, please specify", and a splotch of whitespace in the silkscreen where you can label it w/ a marker... or, you know, just the whitespace and screw jumpers because it gets what it's loaded with.

I'm just throwin' suggestions, tho... and I know little about programming and less about FPGAs etc, so ignore me if I deserve it ;)

  Are you sure? yes | no

androSID wrote 06/17/2020 at 07:11 point

For "Completely custom stuff" you'd need to learn VHDL or Verilog and program the device. Providing a configurator GUI is completely out of question!

  Are you sure? yes | no

Starhawk wrote 06/17/2020 at 08:09 point

I think we may be talking past each other.

What I'm picturing is absolutely *NOT* a sci-fi-esque graphical interface that says "Go hog wild, dude!" with some sort of undoubtedly magical VHDL frontend that lets you take a 6502 core and turn it into whatever ram-horned three-eyed, gills and tentacles and a beak that breaths fire monstrosity one can imagine, using mere mouse-clicks and entirely too much daydreaming.

Actually, what I've got in mind is basically a two-box "wizard" that lets you first choose from a set of preconfigured option "blocks" -- 'x' qty of RAM (in 64byte blocks, max say 512bytes), up to say two onboard parallel I/O ports (of which one can be either a 4bit "handshake" port or a full 8bit port), maybe a simple timer-and-shift-register based serial output with a CPU-flag input à la the Signetics 2650, enable/disable the onboard clock gen stuff (i.e., switchable between phi0-in/phi1-out/phi2-out, phi0-in/phi2-out, or phi1-in/phi2-in from an external source), etc -- and second reconfigure (to a limited extent!) the pinout so that if you eg didn't need SYNC, RDY, S.O., /NMI, and had taken out phi1-out in the clock-gen box, and you also wanted to eliminate the N.C. pins, but you *desperately* wanted an 8bit I/O port with all pins exposed, you could remap things a bit and get that.

Since I have very little understanding of FPGAs and pin multiplexing is probably not a thing on the ones that mere mortals can afford (heck if I know -- that's a WAG, plain and simple, but it's based on what I know of how most manufacturers often think... i.e., only the really expensive toys get the good stuff in 'em), the second box may need to be either really freakin' limited or eliminated entirely (#awkward, as the kids would say).

Meh. I'm talking out my *** as usual. I'm probably being incredibly stupid. You're the expert, you tell me -- I know I'm off my rocker, but by how far...? :D

  Are you sure? yes | no

androSID wrote 06/17/2020 at 08:23 point

Q: "I know I'm off my rocker, but by how far...? :D"
A: Too far! ;-) There won't be a configuration GUI.

  Are you sure? yes | no

Jim Drew wrote 06/12/2020 at 07:43 point

Nice job with this!  It's a lot of work - I know because I have done the same type of 65xx drop-in replacement using a different approach - cycle exact emulation using a high-speed dual core microcontroller (core written in all assembly code).  Besides being able to be pin compatible with various 65xx/85xx derivatives it also can be an accelerator (up to about 48MHz best case).

  Are you sure? yes | no

androSID wrote 06/12/2020 at 07:54 point

In order to speed up the test benches (e.g. Dorman suite) I ran my core with 100 MHz... but I didn't try to go higher.

  Are you sure? yes | no

Jim Drew wrote 06/12/2020 at 18:21 point

Yeah, with FPGA I would think you should be able to crank it up to be much faster than what I am doing.  Of course peripherals typically have to run at a stock speed, so I have a programmable memory map where I can adjust speed between accelerated or cycle exact in 16 byte windows.  That seems to be plenty enough resolution to allow everything to work peacefully.  You can see from the picture below that my board is a lot bigger ( a little more than double the size of a 6502), but I have not found anything that it won't fit in.  I designed it originally as a test bed to debug my stand alone 1541 drive emulator but the stand-up arcade gaming community is pushing it as a diagnostics device because of it's interfaces (serial, OLED, I/O ports, push buttons, and 8MB of RAM for storage).

http://www.cbmstuff.com/images/65xxT.jpg

  Are you sure? yes | no

androSID wrote 06/12/2020 at 19:23 point

Nice... really nice! I also have some plans to make my replacement usable for diagnostics and debugging. But this will most probably take a long time to get these features realized because I also have LOTS of other reverse engineering projects in parallel. Yesterday I ordered a small batch of the latest H/W to check if it's working flawlessly. Keeping fingers crossed!

  Are you sure? yes | no

David wrote 06/10/2020 at 23:16 point

I know this is *not* what you are going for, however, I would simply to like to make the request for a multicore 6502 with 512kb RAM. Now this would require special software to be written to take advantage of it - but maybe following the x86 path of multicores it would not be too difficult (but like someone in a post in this thread - I know nothing about anything or something similar). But I have always thought a 2 core 2 thread 6502 CPU would just rock.

Thanks for your time.

  Are you sure? yes | no

Starhawk wrote 05/29/2020 at 15:59 point

Any recent progress? Just curious :)

  Are you sure? yes | no

androSID wrote 05/29/2020 at 16:06 point

Yes. I soldered one of the new prototypes to check the newly designed power supply. It works great - but we found a minor mistake. This will be fixed in the next 1-2 weeks - as time permits and then we're finally ordering a small batch to go into testing.

  Are you sure? yes | no

Starhawk wrote 05/29/2020 at 16:33 point

Oooh, can it be "configured", as I had suggested elsewhere in these comments? If so, I'd probably be interested in a testing board... :D that would be fun!

  Are you sure? yes | no

Starhawk wrote 06/01/2020 at 00:50 point

Gentle *poke* for response :)

  Are you sure? yes | no

Mathieu wrote 03/11/2020 at 10:12 point

Any chance to get the HDL code for Jim Brain's Fake7501?

I've several C16 to repair and already have Fake7501 PCB.

Many thanks!

  Are you sure? yes | no

Mathieu wrote 05/11/2020 at 06:47 point

Thanks, but it seems you made some changes in it, no?

Original HDL code doesn't works.

  Are you sure? yes | no

androSID wrote 05/11/2020 at 07:03 point

In order to not break any license, copyright or whatever I didn't use/change the code supplied in this repository but did a full new own implementation. However I have no plans to publish this as it was just meant for testing.

  Are you sure? yes | no

Czajnick wrote 02/10/2020 at 11:04 point

What are the buffers you use here? I started similar project a few years ago (see https://pbs.twimg.com/media/Cg6KH_8WwAAkd69?format=jpg&name=large ) but had to abandon it (so called life ;) ). 

  Are you sure? yes | no

androSID wrote 02/10/2020 at 11:57 point

I'm using bus switches instead of buffers. That means  I make the FPGA 5V tolerant but rely on the TTL compatiblity of the target hardware.

  Are you sure? yes | no

Czajnick wrote 02/10/2020 at 12:20 point

Hmm, in fact that was exactly my choice as well - SN74CB3T16210DGG to be axact. Have you seen any issues woth this approach? I had some stability issues, but had no time to debug it.

  Are you sure? yes | no

androSID wrote 02/10/2020 at 12:50 point

So far no issues. All issues I had were related to timing. I only use very weak pull-ups (5kOhm).

  Are you sure? yes | no

ib.video wrote 01/30/2020 at 13:17 point

Fantastic project!! I have the same same question as the user bevore - will the board be available for sale, or are the sources open?

I am just trying to implement the 8501 into a lattice machxo fpga but i am far away from a working implementation.

  Are you sure? yes | no

androSID wrote 02/10/2020 at 11:53 point

The board will be available for sale and later on also be open source.

  Are you sure? yes | no

Johannes Linde wrote 12/25/2019 at 21:40 point

Awesome! For a long time I was thinking of designing a similar board for my Commodore Plus 4 in need of a new 8501 CPU but I did not want to use an obsolete 5V tolerant CPLD/FPGA. I did find the level converters from TI but I never thought of designing a universal board like you did. Great work. Are you planning on selling it soon or to send it out for testing? I would also like to test/buy your PLAdvanced. Greetings from Denmark.

  Are you sure? yes | no

androSID wrote 02/10/2020 at 11:56 point

We're currently refining the hardware.... (hopefully) the last changes before starting a small series production.

  Are you sure? yes | no

Starhawk wrote 12/20/2019 at 06:45 point

@androSID -- disappointed that you don't seem to be around all of a sudden. I hope I didn't chase you off. (If I did -- come back, and I'll make it up to you, *somehow*!) Regardless -- I'd love to see more progress here... ;)

  Are you sure? yes | no

androSID wrote 12/20/2019 at 08:19 point

I'm still here but I'm currently busy with lots of other stuff (e.g. real life) not related to this project. However I finished a long outstanding one just these days: https://hackaday.io/project/169038-smack-smallest-clock-replacement-for-the-c-64

  Are you sure? yes | no

Starhawk wrote 12/20/2019 at 19:24 point

"Life is what happens while you're making other plans..." as my Grandpa Cliff would've said... I can definitely relate ;)

Well, when you get the chance to get back to it, I look forward to seeing and hearing what comes out of it. I'll be here...

  Are you sure? yes | no

androSID wrote 12/20/2019 at 21:19 point

Don't worry... the project hasn't stopped and we're just getting the current prototypes fixed (at least we try to) and at the same time preparing the hopefully final version of the hardware. :-)

  Are you sure? yes | no

Aidan Dodds wrote 11/11/2019 at 22:46 point

I'm so interested in this project.  I'd also love to see a schematic for the hardware as I've wanted to make an 5v tolerant fpga dev board for some time.

Really cool project, and i'd insta buy one (or 10) if it was sold on tindie.

  Are you sure? yes | no

androSID wrote 11/12/2019 at 07:09 point

The schematics will be published once the (hopefully) final hardware is made. But if you need some information beforehand just let me know... My board will also be sold with full information - so everyone can use it to make his own DIL40 replacement part(s).

  Are you sure? yes | no

Starhawk wrote 11/11/2019 at 22:35 point

WANT. (insert jumping coffee mug GIF here)

Dude, the 6508 is rarer than hens' teeth. I've been looking for one in the wild for... at least five years now. Earlier this year I saw *two* on eBay in short succession, and both were out of my price range essentially instantly... and I'd never seen one before and probably won't again for a very, very long time.

The /really/ annoying thing is that I actually sort of have a use for the dang chip. I just can't get one.

You know... this also opens up the possibility of creating custom 6502 variants that all share the same package (40oin DIP) but have various different capabilities... like a 6508 with 256 (or even 512) bytes of RAM instead of 128, for example, which would be pretty dang cool. I don't know much about FPGAs (really I hardly know anything) but I kind of wonder how hard it would be to put together a custom configurator sort of thing, where you could basically roll your own 6502 variant in that package, with a relatively simple crossplatform wizard and the requisite hardware. That would be AMAZING.

  Are you sure? yes | no

androSID wrote 11/12/2019 at 07:14 point

I recently sold 3x 6508R2S on eBay... even in ceramic package. Never thought someone would actually need them except for repairing this old C900? Anyway I'm trying to implement this one (should be quite easy) but I hope to find someone with a C900 in order to make some measurements. I'd like to find out the behavior of the address bus, data bus and R/W# as soon as the internal RAM is accessed.

  Are you sure? yes | no

Starhawk wrote 11/12/2019 at 16:03 point

Hmmm... are you in Munich? The two I saw were sold by the same guy on there, and IIRC that's where he lived... could be wrong. I wrote him as well, at one point... my eBay handle is very similar to my handle here. Would be kind of amusing if you were him ;)

The thing I want to use one for, is inspired, at least in part, by a slightly obscure retrocomputing kit system one can buy nowadays... Lee Hart's "Membership Card" based on the RCA CDP1802 CPU (which is incredibly weird in so many interesting ways) that fits in an Altoids metal mint tin. I want to do something sort of similar -- I figure I can maybe get a hex trainer accomplished, something like the KIM-1, if I do it right -- with a 6502 variant and a 2nd Gen iPod Shuffle's plastic retail box. (I should note, at some point, that I have a couple of very old, very Soviet 8- or 9-digit calculator-style "bubble" displays, to provide a remarkably compact display.) I can't afford proper custom PCBs, but I figure if I can keep the chip count to what will fit on three 5x7cm eBay-issue perfboards, I should be okay. Each of those perfboards is 18 x 24 holes, though, so the lower I can get the chip count in absolutely every way possible, the easier the task becomes. I'm admittedly cheating a little already, since the plan is that the control keypad will be very much external, but I really want everything else to fit in that box...

  Are you sure? yes | no

Starhawk wrote 11/29/2019 at 02:40 point

OH DUH. Sent you a PM.

  Are you sure? yes | no

androSID wrote 07/04/2019 at 07:44 point

It's implemented in a FPGA... the only thing missing right now is finalizing the hardware. I got distracted by other pending reverse engineering projects.

  Are you sure? yes | no

Ken Yap wrote 07/03/2019 at 11:32 point

I take my hat off to your ambition. I am guessing from the tag FPGA that you intend to implement this in a FPGA eventually? Looking forward to it. 👍!

  Are you sure? yes | no

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