- FPGA: Very basic forward propagation. (READY)
- 18F2550: MPU outputs to concatenated PWM signals with timer interrupts. (READY)
- FPGA: MPU PWM duration to value. (READY)
- FPGA: Dynamic network initialization. (READY)
- FPGA: Get max value/action of outputs neurons. (READY)
- FPGA: 1 input, 2 hidden and 1 output layer with 16 neuron per each max. (READY)
- FPGA: Activation functions in hidden layers. (READY)
- FPGA: Bias neurons. (READY)
- FPGA: RL & Backpropagation. (WORKING)
- FPGA: Use MPU PWMs on input neuron.
- Some Test.
- FPGA: MiniBatch.
- FPGA: Dynamic random weight initialization.
- FPGA: Temporal neurons.
- FPGA: To use RAM to augment neurons and weights.
- think more...
October 17, 2019
October 15, 2019
October 9, 2019
Logic elements exhausted on Cyclon IV EP4CE6 (around 6K LEs).
Waiting a DE10-Nano with a Cyclon V and 110K LEs.