Project Logs

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• Layout improvements

  Carson Herrington • 08/04/2019 at 20:56 • 0 comments

  I've had time to work on Amaranth a little more. Since I last documented it, I've more or less finished reworking the board layout to make sense with the PPC603e. Going from the 601v to the 603e allowed me to use a 32-bit bus instead of the unwieldy 64bit bus from before. This simplified the design and just about halved the IC count, all while sacrificing very little.
  
  I have also changed some parts out, mainly the FPGAs I'm using; I have swapped the Altera devices I had previously out for some parts from Lattice. My experiences with Altera chips recently have been very frustrating, to say the least. So they are out.
  
  Most of the part choices are finalized as of now. Things like the CPU and RAM aren't going to change again (unless I find a particular need to waste tens of hours). I'm going to stick with Lattice FPGAs for this project, but I haven't decided exactly which devices I will be using. I'm pretty confident that the part I have chosen now for the main glue is final, but the one for the VGA is almost certainly going to change. My VGA generator code only uses ~60 pins total, which is about half of the total pins on the package; It's complete overkill.

  Also I just want to show off my routing here cause I'm a little proud of this weave:

• Amaranth and the initial state

  Carson Herrington • 07/20/2019 at 13:14 • 0 comments

  As the first project log, here begins the obligatory 'how and why'.

  Is this on hold, is it shelved, what is it?

  Amaranth is certainly alive, and is my main hardware project as of now. After more or less finishing my 68030 homebrew Blitz (write-up still pending currently, but here's an old video until then), I wanted to pursue a different architecture. I was sparked to actually do something when I realized that not only could you get PowerPC chips in QFP, but that they actually weren't that bad price wise on eBay.
  

  Right now, I am busy migrating the schematic and the already partially laid out board to a different CPU: the PPC603e. Previously, I was using the PPC601v, which has a 64bit data bus. I only recently realized that there was a PPC chip that supported a 32bit bus, which I decided was much more within the scope of this project. Aside from that, the hardware is more or less finalized, but is by no means set in stone; Certain bits probably will change as I get further into the datasheets.
  

  Here's the full board layout right now:
  

  As stated in the project details, Amaranth is definitely in the design phase for the most part. I created this project page mainly because I have just started actively working on it regularly again, and expect to have a lot more to talk about as a result.
  

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