I've had time to work on Amaranth a little more. Since I last documented it, I've more or less finished reworking the board layout to make sense with the PPC603e. Going from the 601v to the 603e allowed me to use a 32-bit bus instead of the unwieldy 64bit bus from before. This simplified the design and just about halved the IC count, all while sacrificing very little.
I have also changed some parts out, mainly the FPGAs I'm using; I have swapped the Altera devices I had previously out for some parts from Lattice. My experiences with Altera chips recently have been very frustrating, to say the least. So they are out.
Most of the part choices are finalized as of now. Things like the CPU and RAM aren't going to change again (unless I find a particular need to waste tens of hours). I'm going to stick with Lattice FPGAs for this project, but I haven't decided exactly which devices I will be using. I'm pretty confident that the part I have chosen now for the main glue is final, but the one for the VGA is almost certainly going to change. My VGA generator code only uses ~60 pins total, which is about half of the total pins on the package; It's complete overkill.
Also I just want to show off my routing here cause I'm a little proud of this weave: