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SPAM-1 - 8 Bit CPU

8 Bit CPU in 7400 with full Verilog simulator and toolchain

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SPAM-1 : Simple Programmable And Massive - v1/v2
"Massive" in the sense that it's going to be built on breadboard.

8 Bit CPU using mostly HCT chips and fully simulated in verilog with realistic chip timings.

The current design is a heck of a lot more complex than the original POC but also a lot more capable. Unlike the POC it won't be relying on google sheets as the development effort of programming in that environment is too high, and also because I want to be able to use Icarus verilog and other such tools.

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The prototype learning exercise was simulated in Logisim Evolution with an assembler written in Google Sheets - I've not seen this done before - is it a first? My intention was to make the tooling as accessible as possible and more visual.

However, once that initial effort and sim was completed I decided that this was too trivial to actually build as hardware. So I decided to bite off a lot more.

V2 objective

I got v1 working in the sim but then decided I wasn't going to build it in hardware as these very simple CPU's aren't that capable or complex and I wanted more of a challenge; something that would force me to learn more.

So this has changed out of all recognition.

Along the way I got distrated by a hardware build of a testing device for all the chip's Ive bought for this CPU project. The testing device project can be found in my project list. That was interesting and a throw back to my Uni days in the 80's.

Now, I'm firmly back on the CPU task and nearing the end of the design and sim phase....

UPDATE: After a few more months I've finally settled on the capabilities and design and have arrived at an approach that appeals to my  sense of symmetry. I've adopted some features of ARM; specifically conditional instructions and status flag control.

Check out the project logs !



V1 objective 

⭐️ I wanted to do things a little differently to some of the other efforts on the internet! 

I wanted the assembler and any other code I write to to be more readily accessible and instantly usable to others (like you) without installing python or perl or whatever first, so I've written the assembler in google sheets!I want to be able to run at least the typical demo programs like Fibonacci

  • I would like to extend it to play some kind of basic game (tbd)
  • It will have an assembly language and assembler for it
  • I might port C to it
  • I want to simulate it first
  • I want to build it physically, or a more likely a derivative

  • NES Game controller complete

    John Lonergan10/29/2021 at 00:09 0 comments

    I've added an NES gamepad adapter to the project. This gives me a way to provide interactve input to games and get on with more of the build.

    The implementation is based around a PIC micro which handles the I2C comms with the two gamepads.

    I also needed a random number generator for the games so with a bit of space on the breadboard and a small addition to the design I added that too.

    For more info ...

    Hackaday project for the adapter ...

    https://hackaday.io/project/181036-nes-controller-interface-using-pic16f18446

    As usual I have a verilog simulation of the adapter....

    https://github.com/Johnlon/spam-1/blob/master/verilog/gamepadAdapter/gamepadAdapter.v

    The hardware schematic is ...

    https://easyeda.com/editor#id=c41219d653c64b329350f3ddb47a70a8

    The main routine of the microcontroller code is ... 

    https://github.com/Johnlon/NESInterfaceAndPeripherals/blob/main/main.c

  • Fully wired and working ! New subproject spawned.

    John Lonergan08/01/2021 at 21:30 0 comments

    I wired in the register file, the RAM, the ALU and the memory address registers 

    Did it work?

    No, an error showed up when I tried running the CHIP-8 Tetris program.  

    I spent hours trying to figure our my mistake and in the end it was my wiring of the signals from a 74245 transceiver being off by one pin. Gah !

    Anyway, I happily watched SPAM-1 playing Tetris but without any means to interact with the game and having no random number generator (yet) for CHIP-8 it was a major milestone but limited.

    It has been great though that I have had literally zero timing issues with this CPU that didn't also show up in the Verilog simulation - this has been a great vindication.

    I have two options for integrating a controller into SPAM-1. The first is to provide the hex keypad input via the over the UART as I've done previously and the other is to wire up some games controllers to the hardware; specifically a pair of Nintendo NES controllers. This latter approach helps wean the CPU off the UART interface and eventually I'll add a VGA interface so the UART inteface can be detached entirely.  

    Anyway, to fill in a few of the hardware gaps including the lack of games controllers I've come up with a side project to build a parallel interface adapter to NES controllers.

    This new device will also provide a whole load of other peripheral functions and it's rather akin to how the 6522 complements the 6502.

    Take a look and subscribe for updates.  

  • Almost there!

    John Lonergan07/06/2021 at 01:49 0 comments

    So I've also wired in the Register file now which means I have a total memory of 4 bytes.

    Not a lot but plenty to adapt my trivial UART program to echo back whatever is typed at the console.

    This all seems to work fine at around 2MHz which is where my 555 timer clock maxes out. I'm quite interested to see how fast this thing can be made to run on a breadboard. I'm pretty sure that the critical timing data path is about 200ns half cycle, so I'll see if I can get 5MHz at least from it. The single biggest component in the latency is the 80ns-100ns EEPROM used for the ALU, add to that say another 100ns for other components in th data path and 4-5MHz seems reasonable. It will be interesting to see if the IC's outperform the advertised timings.

    I've also wired up all the ALU status register flags to the control logic so all that's left to hook up is the Memory Address Registers and the 64KB RAM.

    As soon as I have the RAM in place I'll try running some of my MUST more complicated CHIP-8 programs on SPAM-1 CHIP-8 emulator.

    This is a massive achievement for me given I've spent ages building this thing in fits and starts.

    I'll need to add a few more things like a random number generator and an IO port to which  can add something like a games controller. And, the thing I'm really interested in is adding some video RAM and VGA output.

    Anyway lots to come - but I want to get that CHIP-8 stuff working this week if possible.  

  • Check the pinout, stupid.

    John Lonergan07/06/2021 at 01:41 0 comments

    I spent a couple of painful hours trying to figure out why I was getting strange 1.3v signals on some lines that also weren't switching properly.

    I was dealing with a 7402 NOR gate and as you can see below it's pinout is the opposite of basically every other logic chip I have in SPAM-1. 

    Without checking the schematic I'd assumed the 7402 had the more common pinout, so I'd connected output to outputs and inputs to inputs, which helps explain why nothing was working for me last night.

    There's also a reversed NAND the 7401.

    So frustrating - drove me half mad.

  • SPAM-1 It's alive

    John Lonergan05/17/2021 at 16:58 0 comments

    Getting back to wiring up SPAM-1.

    It recently executed it's first "hello world" program compiled from SPAMCC it's C-like high level language - this hello world responded to key presses on the UART stream by piping back "Hello World" to the serial monitor. At present SPAM-1 has no RAM or registers wired, though they are built as you will see in the latter half of this video on the rigth hand side. The lack of RAM/registers means SPAM-1 can't really do much else yet but this proves out that the control logic, timing, decoding and conditional instructions are working fine so far. 

    The hardware around the UART did something strange though - it printed random repeats of the characters I was sending back to the serial monitor. What was actually happening was that an oscillation was setup due to the combination of the gating of a UART /WE input signal with the UART TXE output signal, plus, the particular opcode that I was using to detect that it was valid to write. This feedback loop was easily fixed, however I was surprised (annoyed) because I'd not seen the same behaviour in the Verilog simulation so I went back and looked closer. I was even more surprised to see that I had forgotten that one of my existing test programs for the UM245R verilog model actually demonstrated and relied on this same oscillating behavior - which was comforting in a bizarre sort of way as it showed the hardware and model to actually match.     

    Everything needs wiring into the bus cable now.

  • Videos on SPAM-1 Digital Displays

    John Lonergan05/08/2021 at 11:31 0 comments

    Two videos...

    And the inevitable....

  • Verilog delays

    John Lonergan05/08/2021 at 11:25 0 comments

    if I haven't already highlighted this paper by Clifford Cummings then I should have....

    https://www.researchgate.net/publication/228917496_Correct_Methods_For_Adding_Delays_To_Verilog_Behavioral_Models

    You will hopefully be aware that I have a complete behavioural simulation of SPAM-1 in Verilog (suggested by Warren Toomey aka Dr WKT) .

    The simulation is as far as I can make it also timing accurate for the chips I've used in the hardware.

    This paper above was instrumental in my understanding (a bit) how timing works in Verilog and helped me decide to go for a "Transmission delay" approach because that is most aggressive in highlighting glitches if there are any. My entire model hasn't yet switched over.

    Really important for folk to understand if hoping to get the most from a model.

  • Bus Indicators

    John Lonergan04/12/2021 at 18:36 0 comments

    Anyone interested in how I'm displaying the 8 bit values of my busses should look to one of my other projects ... https://hackaday.io/project/178227-7-segment-module-using-pic16f18446

  • Be Negative

    John Lonergan04/01/2021 at 19:18 0 comments

    The conditional instructions in SPAM-1 are based on the various state flags; carry, negative, equal, greater than, data in ready, data out ready and so on.

    With the exception of "not equal" all the checks are positive , eg "do exec if equal" , or "do exec if data ready"

    I didn't realise before that this seems to lead to more code bloat than negative logic, eg "do instruction if data Not ready"

    I found myself writing something like this frequently...

    Top:
    
         If data is ready then jump to Handle:
    
         Jump to Top:
    
    Handle:
    
         -- do stuff

    With negative logic I get...

    Top:
    
       If data not ready then jump to Top:
    
       -- do stuff

    I don't know anything about research on this but is it the case that most of the time your design is better off with negative logic? Some CompSci person must know.

    This is the kind of question I started this project to provoke.

  • 50% of final assembly, so the hacking starts

    John Lonergan03/13/2021 at 19:04 0 comments

    Half of the CPU hooked up and then I realise there's no space for a single AND gate that I needed for the program counter. control logic.

    I needed a solution, then I realsed that I had some 1N4148 diodes decided to have a go at some "diode logic" to add some variation to the implementation. There was a tiny bit of spare space at the end of the control logic and so ....

    I referred to this paper to understand the principles as bit better  http://www.uobabylon.edu.iq/uobColeges/ad_downloads/4_22382_163.pdf

    I then simulated the AND gate it on (free) Microcap 12 as shown in the screenshot below to see how the logic levels would look. Getting a low of about 300mv and a high of over 4v I decided that it was sufficient. 

    D2 and D1 below are the AND gate inputs and the output is via diode D2. Reading the PDF again I think I now understand why the design I was looking at had two diodes in series at the out where below I have only a single diode D2. I think it's so that it is guaranteed that the forward voltage of the output path (ie D2) would be greated than that of the the inputs. I think was to ensures that the output is biased off properly when one of the inputs is low. It prevents any current flowing to the output. I'll see how it goes without it.  

    You can see the three diodes the two resistors crammed into three lines on the breadboard below.

    (Spot the iwiring mistake)

    Fingers crossed. 

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