SPAM-1 - 8 Bit CPU

8 Bit CPU in 7400 with full Verilog simulator and toolchain

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SPAM-1 : Simple Programmable And Massive - v1/v2
"Massive" in the sense that it's going to be built on breadboard.

8 Bit CPU using mostly HCT chips and fully simulated in verilog with realistic chip timings.

The current design is a heck of a lot more complex than the original POC but also a lot more capable. Unlike the POC it won't be relying on google sheets as the development effort of programming in that environment is too high, and also because I want to be able to use Icarus verilog and other such tools.


The prototype learning exercise was simulated in Logisim Evolution with an assembler written in Google Sheets - I've not seen this done before - is it a first? My intention was to make the tooling as accessible as possible and more visual.

However, once that initial effort and sim was completed I decided that this was too trivial to actually build as hardware. So I decided to bite off a lot more.

V2 objective

I got v1 working in the sim but then decided I wasn't going to build it in hardware as these very simple CPU's aren't that capable or complex and I wanted more of a challenge; something that would force me to learn more.

So this has changed out of all recognition.

Along the way I got distrated by a hardware build of a testing device for all the chip's Ive bought for this CPU project. The testing device project can be found in my project list. That was interesting and a throw back to my Uni days in the 80's.

Now, I'm firmly back on the CPU task and nearing the end of the design and sim phase....

UPDATE: After a few more months I've finally settled on the capabilities and design and have arrived at an approach that appeals to my  sense of symmetry. I've adopted some features of ARM; specifically conditional instructions and status flag control.

Check out the project logs !

V1 objective 

⭐️ I wanted to do things a little differently to some of the other efforts on the internet! 

I wanted the assembler and any other code I write to to be more readily accessible and instantly usable to others (like you) without installing python or perl or whatever first, so I've written the assembler in google sheets!I want to be able to run at least the typical demo programs like Fibonacci

  • I would like to extend it to play some kind of basic game (tbd)
  • It will have an assembly language and assembler for it
  • I might port C to it
  • I want to simulate it first
  • I want to build it physically, or a more likely a derivative

  • SPAM-1 It's alive

    John Lonergan05/17/2021 at 16:58 0 comments

    Getting back to wiring up SPAM-1.

    It recently executed it's first "hello world" program compiled from SPAMCC it's C-like high level language - this hello world responded to key presses on the UART stream by piping back "Hello World" to the serial monitor. At present SPAM-1 has no RAM or registers wired, though they are built as you will see in the latter half of this video on the rigth hand side. The lack of RAM/registers means SPAM-1 can't really do much else yet but this proves out that the control logic, timing, decoding and conditional instructions are working fine so far. 

    The hardware around the UART did something strange though - it printed random repeats of the characters I was sending back to the serial monitor. What was actually happening was that an oscillation was setup due to the combination of the gating of a UART /WE input signal with the UART TXE output signal, plus, the particular opcode that I was using to detect that it was valid to write. This feedback loop was easily fixed, however I was surprised (annoyed) because I'd not seen the same behaviour in the Verilog simulation so I went back and looked closer. I was even more surprised to see that I had forgotten that one of my existing test programs for the UM245R verilog model actually demonstrated and relied on this same oscillating behavior - which was comforting in a bizarre sort of way as it showed the hardware and model to actually match.     

    Everything needs wiring into the bus cable now.

  • Videos on SPAM-1 Digital Displays

    John Lonergan05/08/2021 at 11:31 0 comments

    Two videos...

    And the inevitable....

  • Verilog delays

    John Lonergan05/08/2021 at 11:25 0 comments

    if I haven't already highlighted this paper by Clifford Cummings then I should have....

    You will hopefully be aware that I have a complete behavioural simulation of SPAM-1 in Verilog (suggested by Warren Toomey aka Dr WKT) .

    The simulation is as far as I can make it also timing accurate for the chips I've used in the hardware.

    This paper above was instrumental in my understanding (a bit) how timing works in Verilog and helped me decide to go for a "Transmission delay" approach because that is most aggressive in highlighting glitches if there are any. My entire model hasn't yet switched over.

    Really important for folk to understand if hoping to get the most from a model.

  • Bus Indicators

    John Lonergan04/12/2021 at 18:36 0 comments

    Anyone interested in how I'm displaying the 8 bit values of my busses should look to one of my other projects ...

  • Be Negative

    John Lonergan04/01/2021 at 19:18 0 comments

    The conditional instructions in SPAM-1 are based on the various state flags; carry, negative, equal, greater than, data in ready, data out ready and so on.

    With the exception of "not equal" all the checks are positive , eg "do exec if equal" , or "do exec if data ready"

    I didn't realise before that this seems to lead to more code bloat than negative logic, eg "do instruction if data Not ready"

    I found myself writing something like this frequently...

         If data is ready then jump to Handle:
         Jump to Top:
         -- do stuff

    With negative logic I get...

       If data not ready then jump to Top:
       -- do stuff

    I don't know anything about research on this but is it the case that most of the time your design is better off with negative logic? Some CompSci person must know.

    This is the kind of question I started this project to provoke.

  • 50% of final assembly, so the hacking starts

    John Lonergan03/13/2021 at 19:04 0 comments

    Half of the CPU hooked up and then I realise there's no space for a single AND gate that I needed for the program counter. control logic.

    I needed a solution, then I realsed that I had some 1N4148 diodes decided to have a go at some "diode logic" to add some variation to the implementation. There was a tiny bit of spare space at the end of the control logic and so ....

    I referred to this paper to understand the principles as bit better

    I then simulated the AND gate it on (free) Microcap 12 as shown in the screenshot below to see how the logic levels would look. Getting a low of about 300mv and a high of over 4v I decided that it was sufficient. 

    D2 and D1 below are the AND gate inputs and the output is via diode D2. Reading the PDF again I think I now understand why the design I was looking at had two diodes in series at the out where below I have only a single diode D2. I think it's so that it is guaranteed that the forward voltage of the output path (ie D2) would be greated than that of the the inputs. I think was to ensures that the output is biased off properly when one of the inputs is low. It prevents any current flowing to the output. I'll see how it goes without it.  

    You can see the three diodes the two resistors crammed into three lines on the breadboard below.

    (Spot the iwiring mistake)

    Fingers crossed. 

  • DOH! Much simpler ZIF socket extender

    John Lonergan02/10/2021 at 02:49 0 comments

    I was looking at my 32 pin ZIF sockets tonight and I noticed that while the pins are too short to be secure in a breadboard they were long enough to fit snugly into some extra long stackable female pin headers that I have.

    This is such a simple solution to the two problems I had, firstly the problem mounting ZIFs securely in breadboard and secondly the need to get some clearance between the ZIF and the breadboard.

    The clearance was needed to allow space for all the surrounding wiring.

    I had 10 of the 8 pin headers but since I need 4 per device I just bought a bunch more of the stackable headers from the

    These are an excellent length and the socket fits really securely and of course the breadboard fit it rock solid. 

    I now have clearance to run wires directly under the sockets.


    Using the few headers I have spare .

    ROMs on stilts

  • Hadn't realised how bad my ready made wires were!

    John Lonergan02/08/2021 at 22:24 0 comments

    Just got some fab new wires ...

    Brand: Seeed Studio
    Part Number: PPCAB110C4M

    Pack of 65 for £1.98, so I bought three packs and will ditch my old ones.
    Postage adds a couple of quid

  • Control and ROM underway

    John Lonergan02/07/2021 at 04:28 0 comments

    Finally getting progress again but not without setbacks. I had the ROM address lines all hooked up but then tore them out again today when I realised the next change I was about to make wouldn't fit.

    I've decided to put the ROMs in ZIF sockets. But the existing chip position didn't leave enough  space for the bigger footprint of the ZIF so I tore out the wriring and moved stuff around.

    Even now the ZIF will not fit  because it's wider footprint will collide with the wires. But I think I have fixed this with a trivial extender adaptor board for the ZIF so it sits proud of the breadboard. 

    The adaptor is and the idea is that it puts the ZIF on stilts by using very long pin headers to attach to the breadboard. To be honest in retrospect this would have been pretty easy on veroboard rather than getting PCBs made up.

    Maybe 25% of control logic done.

    Getting closer to integration!?

  • Coming together

    John Lonergan01/31/2021 at 21:14 0 comments

    Program ROM and control logic module needs building as you can see in the photo below.

    The "ROMs" I am using are flash devices SST39SF010 128KByte and I'll only use 64K. Detailed board layout to follow. May lead to moving the clock module to the right hand column. We'll see.

    I also want to find space for an indicator block with 7 seg displays showing the 3 ALU busses at least and possibly PC address as digits. I have an idea to build some 8 bit parallel to dual 7 seg modules.

    Original paper layout...

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