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A project log for SPAM-1 - 8 Bit CPU

8 Bit CPU in 7400 with full Verilog simulator and toolchain

John LonerganJohn Lonergan 04/01/2021 at 19:180 Comments

The conditional instructions in SPAM-1 are based on the various state flags; carry, negative, equal, greater than, data in ready, data out ready and so on.

With the exception of "not equal" all the checks are positive , eg "do exec if equal" , or "do exec if data ready"

I didn't realise before that this seems to lead to more code bloat than negative logic, eg "do instruction if data Not ready"

I found myself writing something like this frequently...

Top:

     If data is ready then jump to Handle:

     Jump to Top:

Handle:

     -- do stuff

With negative logic I get...

Top:

   If data not ready then jump to Top:

   -- do stuff

I don't know anything about research on this but is it the case that most of the time your design is better off with negative logic? Some CompSci person must know.

This is the kind of question I started this project to provoke.

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