The FEMU (Femto's ESP32 ModUle) fits inside a typical USB Type-A port. The design includes an LDO regulator, an FTDI chip, an ESP32-D2WD (2MiB), and a GND + 3V3 + DAC pin on the curved edge. Note: this design uses micro vias, blind/buried vias on a 4 layer board!
Ok, so after working with Mike M. Volokhov (@mishkathebear on Twitter), it seems design 1.0.4.ty.01005 is a no go for Wi-Fi. If I understood correctly, it resonates at too high a frequency (sorry, I'm still learning). Here's the Smith chart and SWR, MAG plots with the current chip antenna and footprint.
...I will have to make another FEMU revision without the cutout, and attempt to make a more suitable ground plane clearance, perhaps with a different chip antenna.
Hello everyone! Thanks to the overwhelming community support, this PCB revision is now being fabricated at PCBWay as of the time of this writing!
The RF antenna trace and wave guide has been revised to work with an SMD monopole chip antenna. The RF Trace impedance was too high in 1.0.3, so for 1.0.4, it has been redesigned to be 0.5mm wide, and have an impedance of 35ohm+10j (as per the ESP32-D2WD datasheet notes). A wave guide calculator has been used.
Once this order of FEMU 1.0.4.ty.01005 arrives, I'll need to test and match the RF design using a NanoVNA v2 (also thanks to community support!) while profiling the power usage with the JoulScope (thanks to JouleScope for lending me one for a bit!)
Next couple of batches need to be manufacturered with 1oz and 2oz copper pour, different ground plane configurations, and different chip antenna types!
One set of prototypes will run around $570 (1oz copper pour), while the 2oz copper pour variant will be a bit more than $570, totaling a bit over $1140 for both.
Current version 1.0.3 boards (0.8mm thick, 1oz copper) are mostly functional, but require ground plane adjustments (28cm max BT transmission at best). Currently experimenting with different antenna configurations.
FEMU 1.0.3 has a revised RF layout and ground plane, along with more copper pour for the LDO footprint. I've also managed to break out both DAC pins. Currently testing the LDO at max throttle via the 2-layer prototype (larger, but same components).
I've also figured out how to use ftdi_eeprom to adjust the behavior of the DTR and RST pins, and finally got the FT232XQ-R working nicely.
At the very least, I've fixed the botched UART lines. I am able to flash MicroPython on to the FEMU. Unfortunately, I'm running into trouble trying to get REPL working with the latest esp-tool and MicroPython code base. I am going to troubleshoot it some more, but things seem to be manageable.