Addressing modes

A project log for Kobold K2 - RISC TTL Computer

A 16 bit RISC computer with video display, from just a few TTL and memory chips.

roelhroelh 09/14/2019 at 18:212 Comments

This 16 bit processor has a 20 bit address bus. How is this address generated ?

Around 40 years ago, developers of the Intel 8086 were facing the same problem. This time, we will use an easier solution. But I doubt if my solution will be more succesful.

In the Kobold K2, memory can be accessed with the following addressing modes:


Each of the four address registers has its own 4-bit page register. A page register can be written with a MOVP instruction. 

The memory address consists of bit 0-15 coming from the address register and bit 16-19 coming from the corresponding page register.

In instructions that use this mode, the displacement should be set to zero.


This is considered the main addressing mode. In this mode, the 4-bit displacement value in the instruction is added to bit 1 - 4 of the address. There is no carry from bit 4 to higher bits.

In C terms, the address register can contain a pointer to many different structure instances. Each structure has a maximum of 16 word-sized members. The instruction can specify which member is addressed. This supports the "->" operator in a single instruction.

Register A1 is intended to be used as 'workspace pointer', pointing to a set of 16 locations that can be used as local variables in a function. When a function is called, the workspace pointer can be set to a new value to get a fresh set of variables, so it is not needed to push the old ones on a stack one by one.

As you can see in the picture, there can be seven W bits to define the workspace so 128 sets of registers are available.


There is also absolute addressing. Only short addresses, that are a part of the 16-bit instruction, are supported. It is called Zero page addressing because the upper part of the address is always zero. The instruction delivers the bits VPPDDDD, for a range of 128 locations. (But when the destination of the instruction is A0-A3, the V bit has restrictions). Note that this mode also uses the value of several workspace pointer bits.


The K2 is designed as a 16 bit processor that reads or writes 16 bits from/to memory at the same time.

In order not to exclude languages like C, support for 8-bit characters was added. Therefore, the K2 can address bytes or words in memory. The address in bit 0-15 is a byte address, so for accessing words, addressbit A0 is always zero.

For 8-bit instructions that read or write memory, the lowest address bit determines if the low or high byte in memory is used. The K2 is little-endian.

However, to keep component count reasonable, a little software effort will be needed to read or write bytes:

Note that the processor registers will always contain words.


Dave's Dev Lab wrote 10/11/2019 at 17:55 point

i love the level of documentation you are doing on this build! keep it going!

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roelh wrote 10/11/2019 at 18:06 point

Thanks Dave ! BTW how is your WITCH replication doing ?

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