Super Micro Relay Computer

Going back more than 100 years, in the very early beginning of electronic computing!

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The computers built with relays had an effimerous life, but boldly marked the transition from the mechanical world to the modern electronic era.

Interest among retrocomputing enthusiasts is recently increasing and reasons are many:
- Relays are among the simplest electronic components and this make easier to understand the very basic and very internal processing mechanisms
- The design is based on modern patterns (registries, ALU, RAM, program/ROM/control logic/flags/conditional jumps, etc)
- Is possible to hack on them with extremely limited basic equipment
- They are fun to build and to run, and there is more poetry in seeing and hearing things moving than in the silence and immobilty of the silcon based ones!

This project would like to propose a very "minimal" but still powerful design, buildable with tools and components available in the middle of the 1800, but also affordable and easily replicatable in our time.

Building a relay based computer is surely the ultimate retrocomputing experience, and  my wish is to try to engineer what could have been the very first electronic computer.

With this build I will also try to teach to my daughter some concepts regarding computers that are difficult to see from an high level perspective, and hope also others will find it useful fun and educational!

The goal of this particular implementation is trying to minimize the number of relays removing all possible redundancies still maintaining all the characteristics of a general purpose modern computer. New optimal designs have been already proposed for ALUs (, and here there is a similar continuation for the rest of the computer.

Less relays means a cheaper project, but also easier and faster to build and less space consuming (pretty important in mine but surely many other cases).

Below the "high level" architecture:

Please note that the 2 registers are called Q and R instead of the usual A and B just to avoid confusion with the ones described in the ALUs that are usually both input ones, while here R is the result register (that contains also the carry flag).

One of the key design differences among many of the current proposals is the utilization of punched tape for the program input. The main reason to opt for this choice is the obvious fitting with the period, but there are many others:

- Possibility to simply easily add more control signals simply adding more "hole columns" if needed
- No need for an external clock, since is embedded in the punched signals themselves; and this means less relays
- Easy sub shifting of the individual signal timing, and this means no need of complex clock circuits and more relays
- Possibility to easily regulate overall speed, simply changing speed rotation
- Writing directly signals there is no need for decoding logic; this means fewer relays but also faster execution
- Primitive and inexpensive technology available even before the period
- No limit of program length
- No need of PC counter and separate bus; this means fewer relays, even though there is the need for circuitry to manage the jump instructions
- Faster than manual program input (e.g. with switches) and more elegant and appropriate than EPROM inputs

Surely the fact that there are not already ready modules and a custom build is required is a cons, but the willingness to avoid using more modern technologies is a key factor. Anyway I hope to be able to find an easily buildable solution, and in internet there are already very simple ones to take inspiration from.

For the branch execution management circuit I will fully reuse the ALU (that has an arrangement thought also for this purpose), saving dedicated relays. The control will happen with some parallel dedicated signal support (saving firmware logic and more relays).

Again trying not to use silicon based solutions, regarding RAM I'm working on an original design based on capacitors. The direct memory access (with addresses coming directly from the program) reduce even more the relay count without really affecting programming potential.

Output will be visible on registry relays lamps. Punching cards would be very nice, but this might be a very last addition since the device will not be so simple to be built at home. Instead there will be probably the interface with a parallel printing device. An audible buzzer is completing the capabilities.

On the input side there are a set of switches addressed as the memory and a button to restart execution after halt instruction. More inputs can be read halting the execution between them.

The PC can be microprogrammed in order to have full control and optimization possibilities. Anyway at «high level» the instructions can be represented as:

"data moving"

- Q = R
- Q = Memory[address]
- Memory[address] = data
- Memory[address] = R


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  • Slow but steady progresses

    Stefano10/20/2020 at 20:58 0 comments

    Long time has passed since last post, but things were moving, even if slowly.

    In the meantime I decided to switch to relay socket bases, since faston connections were really too dense to be managed at the scale required.

    I also simplified even more the schema avoiding backward jumps: anyway I would not mechanically build them now, and I implemented them as forward jumps on a looped punch tape. This change would be noticeable in nested loops for very long programs but for now there are no plans for that (and in case I can implement it later).

    The new schema is as follow (in the azure disks the numbers of relays):

    Totaling for a record 46 relays. And no diodes.

    The memory design is still open even if I already bought the required capacitors.

    With the bases the ALU needs a new connection cabling schematic (note that since relais are now seen from the top and not from the bottom as before, the bits endianness is increasing from right to left). Below a single bit slice with carry:

    This is the current work in progress:

    And the relay placement matrix:

  • Click clack

    Stefano11/07/2019 at 08:42 0 comments

    The good news is: the first bit of the Q register and the ALU have been wired and they're working! Also proving that the more efficient ALU designs are a reality!

    I tested for convenience the full adder and for the logic part the NAND operation, but all other logic ones are straightforward to see operating.

    Below for example 1 of the Q register is added to 1 of the bus and a 1 carry in, resulting in a one on a "flying" bit of the R register and a carry out on second bit (note that relay view is upside down):

    The bad news is that mounting it with fastons as I did is extremely difficult with "dense" relay utilization...

    Faston are hard to slot in, and there is very little separation between them with even the risk of a short circuit on the bottom if two adjacent ones are slanted towards each other.

    Boefore continuing to mount the rest of the circuit I've to decide how to mount it. Options might be:
    1. Continue in this way, maybe finding a way to at least prevent short circuits (e.g. with a plastic foil between adjacent connected row of fastons)
    2. Solder the wires to the relays instead of using faston
    3. Buy relay bases and "easily" screw the wires (trashing all the effort spent on the frame, adding one month shipping time to the additional money to be spent)

  • Planning the layout

    Stefano10/28/2019 at 20:08 0 comments

    The frame start to get populated:

    50 might be a little number of relays but surely is already providing quite an intricate mess of wires and a lot of headaches if not properly planned (and even if properly planned): at least let's try to manage at best!

    Following a bit more detailed overall schema of the PC (more details of the various circuits will come in later posts):

    And below a tentative to put some order between units in the frame:

    As of last image a drawing guide for the wiring of the first bit of the ALU (the famous "no dollars" one of @roelh):

    (the full layout of the MY4NJ can be found in first project log)

  • Quality check

    Stefano10/28/2019 at 07:05 0 comments

    First things first: let's start to see if the relays are properly working...

    For the purpose I built a little tester rig:
    Result? Bad. Out of the 62 relays I've found that 13 of them work unreliably and 3 not working properly at all. Partly good news is anyway that I've 46 remaining that seems working, let's see.

    In the meantime I built also a frame to keep the relays of the mounted computer. Here the last assembly step:

  • Let's start!

    Stefano10/20/2019 at 17:33 0 comments

    Relays finally arrived, and now it's time to start build the computer!

    I was liking transparent relays, where you can see the mechanism moving, and I found them at bargain price online. Buying SPDT, DPDT and 4PDT was practically same amount of money, so I selected all of them 4PDT, that will give also a uniform looking. Moreover 12V DC was the minimum available, and I’ve seen that this is a pretty common choice among other implementations. Looking at them afterwards they seems similar to the Harry Porter’s ones!

    I bought around 60 of them, hoping even to spare few with 8bit implementation... In reality I might spare even more realizing at least the first version with 4bit word lenght: easier to assemble, to debug, and anyway reaching all goals of the project, and "expanding" it later. I will decide building it. Anyway the design allows for the word to be any multiple of 4bit (e.g. 8, 16, 32 and even 64 bits) since there is no delay accumulation increasing the word size.

    The relays number in this moment do not account for the memory. For which I will probaly buy a different type (trough hole) for easyness of assembly with condenser (if the current design will work).

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