Long time has passed since last post, but things were moving, even if slowly.

In the meantime I decided to switch to relay socket bases, since faston connections were really too dense to be managed at the scale required.

I also simplified even more the schema avoiding backward jumps: anyway I would not mechanically build them now, and I implemented them as forward jumps on a looped punched tape. This change would be noticeable in nested loops for very long programs but for now there are no plans for that (and in any case I can easily implement it later).

The new schema is as follow (in the azure disks the numbers of relays):

Totaling for a record 46 relays and nothing else (no resistors, no capacitors, no transistors and no diodes) apart a big mess of wires! :)

The memory design is still open even if I already bought the required capacitors.

With the bases the ALU needs a new connection cabling schematic (note that since relais are now seen from the top and not from the bottom as before, the bits endianness is increasing from right to left). Below a single bit slice with carry:

This is the current work in progress:

And the relay placement matrix: