monsoniteSuite-16
Suite-16 arose from my curiosity regarding how computers work.
I have had a lifetime in hardware engineering but very little real exposure to firmware and software since my Z80 coding days in the 1980s.
The Suite-16 project will encourage me to explore the interactions of hardware, firmware and software - hopefully widening my horizons, learning new skills and achieving the goal of building a working TTL computer system.
Suite-16 refers literally to the suite of deliverables needed to put together a working 16-bit computer system.
The main deliverable will be a 16-bit computer system designed and built from 7400 series TTL integrated circuits outlined in the next section below.
From a hardware point of view this will include circuit schematics, pcb layouts, timing diagrams and test-bench programs. It will also likely contain FPGA prototypes with their supporting designs coded in verilog. Part of the project aim is to become familiar with FPGA design and verilog programming - and what better way than to set the goal of a working computer system.
As any computer is the co-ordinated interaction between hardware and software - there will be several key software deliverables needed to complete the design. These will include the Instruction Set - Architecture or ISA, an assembler and a software simulator of the proposed machine. Later on, when the machine is debugged and can run simple code - there will be applications to be written such as high level languages.
You can find my Github repository here: Suite-16 This is updated regularly to include all the latest Arduino code and sketches.
In summary, Suite-16 is an exploration of the knowledge space bounded by hardware, software and FPGA design.
Main Features
Principle Technology: 5V TTL logic with conventional through-hole DIL packages wherever possible
Data bus: 16-bits
Address bus: 16-bits - with possible extension to 24-bits
Architecture: Von Neuman Accumulator-Register
Hardwired Logic - no microcode
Basic 2 stage pipeline allowing most instructions to complete in 1 clock cycle
Registers: 16 general purpose registers R0 to R15. R0 is the accumulator, most ALU operations are on Accumulator and a Register
Additional Registers: Program Counter PC, Instruction Register IR
Number of instructions: 31
ALU Instructions: ADD SUB INC DEC COM AND OR XOR
Memory and Register Instructions: SET LD ST LD@ ST@ POP PUSH
Program Flow: CALL RET JMP BRA and conditional branching BGT BLT BNE BEQ BGE BLE
Other Instructions: IN OUT SRA SLA CLA STC CLC
Addressing Modes: Immediate #N, Register Direct Rn, Register Indirect @Rn, Indirect Autoincrement @Rn+, Indexed Mode (Rn+X), Symbolic Mode (PC +X)
Instruction Length: 16-bits
Instruction Format: 8-bit bytecode in IR 15:8 augmented by 8-bit payload in IR 7:0
Hardware: ALU based on 4-bit bitslice design. ALU + PC plus register file on one pcb. Memory and mass-storage on 2nd pcb.
Performance: Aiming for 12.5MHz clock frequency to have some interoperability with VGA video systems.
Target Use: Co-processor / Accelerator for accompanying TTL colour computer (Gigatron)
Tools and Resources.
Throughout this project I will need to learn new techniques and use new tools.
Hardware simulation will be done using H. Neeman's "Digital" simulator - which is an updated version of Logisim https://github.com/hneemann/Digital
Most of my C code will be run on Arduino compatible platforms - so that it can easily be explored.
For hardware schematics and pcb layout, I generally use EagleCAD 6.x - but I am slowly moving towards open source tools including KiCAD and the online pcb design package from easyEDA https://easyeda.com/
Sometimes we have to resort to FPGAs and a suitable hardware description language such as VHDL nor Verilog to develop complex hardware.
Fortunately there are low cost FPGA boards available and an ever increasing portfolio of open source tools for FPGA design.
I will be planning using Clifford Wolf's "Project IceStorm" open-source toolchain that runs on all platforms and works with Lattice ICE 40 FPGAs. The final hardware will be TTL - but what is wrong in learning how to design for modern FPGAs along the route?
Inspirations and Influences
Throughout this project, I have gained inspiration from others that have worked on similar projects. This has been invaluable in giving me the momentum to start this major undertaking.
Notably there are other enthusiasts on Hackaday.io who have produced TTL computers
This include Marcel van Kervinck with his very successful 8-bit Gigatron TTL Computer, and Roelh with his Kobold series of machines.
Other ideas and inspiration come from Dieter Muller of 6502.org for his design of the TTL ALU which uses multiplexers, and members of the anycpu.org discussion forum.
The OPC Challenge (One Page Computing) featured on Hackaday in 2017 https://hackaday.io/project/25357-opc-1-cpu-for-cpld - featured a family of processor designs intended for CPLD and FPGA, and offered significant insight into what can be achieved with limited resources.
In a similar style, I have tried to keep my development tools simple - and my simulator is just 58 lines of C code.
Historical Influences
The project has an air of RetroComputing around it. It harks back to the age of the minicomputer - when hardware had to be a lot simpler, and all sorts of neat tricks were used to get the most from minimal hardware. Some of the ideas, including zero page addressing and OPR instructions are taken directly from the PDP-8. A good PDP-8 introductory article is here:
The inclusion of multiple general purpose registers evolved a few years after the PDP-8, with its successor the PDP-11. It might be said that Suite-16 is a 16-bit extension to the PDP-8, the sort of machine that might have arisen from PDP-8 Design Engineer, Edson de Castro, had he not left DEC to found Data General and produce the DG Nova.
Finally there is the genius of Steve Wozniak - who's Sweet-16 virtual cpu for the 6502 on the Apple II, inspired a large part of the ISA.
Project Logs
These will generally document the course of the project - and be updated to reflect major changes.
The first 8 logs listed below are basically a BrainDump during the first week of the project - to try to capture the essence of the project so far.
I have arranged them in an order that will make better sense, than the true chronological order in which they were written.
"Simulating the Instruction Set" and "Simple Assembly Tool" refer to practical work that was done in C++ on an Arduino compatible board. The code for this will be available later on my Github project Repository
Exploring the Instruction Set Architecture
More about the Instruction Set
Simulating the Instruction Set
Hardware - Explaining the Bitslice Design
Benchmarking the Suite-16 Simulator
A Table Driven Assembler for Suite-16