Addressing Modes

A project log for Suite-16

Suite-16 is a 16-bit cpu built entirely from TTL. It is a personal exploration of how hardware and software interact.

monsonitemonsonite 10/16/2019 at 14:370 Comments

Modern processors have a wide variety of addressing modes which give the processor its flexibility and also complexity.

The very early processors, before about 1970 had far fewer addressing modes - which resulted in them being more challenging to program, as it would take several operations to achieve simple addressing operations.

I'm hoping to reach a balance between programability and complexity - and this will be down to choosing the most useful addressing modes - and finding an easy way to implement them in hardware.

The various addressing modes evolved over the decades with each new generation of machine.

Originally a Load-Store architecture was  chosen for its simplicity, and the very fact that it didn't need expensive registers or a complex instruction set. This made it popular in the 1960s when hardware (transistor based) was still very expensive. At first, the only addressing mode was memory direct - where the address of the memory to be accessed was embedded as a bit-field within the instruction word. This severely restricted the span of memory that could be addressed to a small page of bytes, or meant that the instruction word-length had to be very long. 

The next innovation was to use a level of indirection.  Whilst you could only directly address a page of say 128 words, with indirection you could access a location of memory on the page that contained the absolute 12-bit address of the memory that you actually wanted to address. This method greatly increased the usefulness of the machine - without over-increasing the complexity of the hardware.  That's why indirect memory addressing arrived with the early minicomputers of the mid-1960s, such as the best selling PDP-8 which initially could access 4096 words of memory using this technique.

Suite-16 uses 16 general purpose 16-bit registers, and this gives it a lot more capability than the traditional Load-Store architectures of the past. The registers may be considered to be a few words of memory that are close coupled to the ALU and can be accessed within the same ALU cycle - without having to address slower external memory.  By the late 1960s new 16-bit minicomputers were appearing on the market - such as the PDP-11 and the Data General Nova and were starting to make heavy use of multi-register architectures. The PDP-11 had 8 general purpose registers, whilst the DG Nova had four accumulators, any of which could be the operand source or destination.

A description of the DG Nova ISA is here

So with locally available registers, you can either use the register's contents directly as the operand, or indirectly, by using it as the ad dress of where the operand is stored. This simple innovation gives us two of the most commonly used addressing modes:

Register Direct

Register Indirect

On Suite-16 I intend to use bit 14 of the instruction register to indicate whether to use direct or indirect addressing modes. Bit 12 of the Instruction register will signify whether the operation is a Load or Store operation.

The next useful addressing mode is indexed addressing. Here a register Rn can be used to form a base address, which can be augmented by a value X. The memory address that we access is given by (Rn + X) By incrementing X we can successively index into a table of data. Indexing is often used to select the nth item from a table of data.  Sometimes however X is held constant and it is the value in Rn which is incremented (or decremented).

Indexed Addressing is often denoted X(Rn) - which signifies that the address held in Rn is modified by X.  In Suite-16 we have the 8-bit payload encoded into the lower byte of the Instruction Register.  This is an ideal place to locate the index X.  If X=0 then the value of Rn goes unmodified.

A close cousin of Indexed Addressing is Symbolic Addressing.  Here it is the PC that is modified by X forming the effective address  (PC+X). If the PC is a general purpose register then Indexed mode X(PC) is the exact equivalent.  Symbolic Addressing provides a convenient way to create look-up tables.

There are times that you wish to perform program branches or sub-routine calls, over the full addressing range of the memory.  Whilst an 8-bit constant X can be used to provide short branches or calls within the same page of memory, by adding X to the PC, long Calls or Branches will require the PC to be reloaded with a completely new 16-bit value. As there is no room in the current instruction to package a 16-bit value it has to follow on in the next memory location. The word following the instruction contains the absolute address - and for this reason the mode is called Absolute Addressing  - often denoted in assembly language as &ADDR.

There remains at least two more useful addressing modes, which came in to popularity with the PDP-11.  They are useful for accessing stack structures - where the contents of the register is a pointer to an address in the stack - otherwise known as a Stack Pointer or SP.  Sometimes there is a dedicated SP register that solely has access to the stack, but in an architecture with several general purpose registers, any one of them could be used to point to a stack, and several separate stacks could thus be created within memory. 

Stacks operate on a last-in, first-out principle, and the only item on the stack which is accessible to the system is the item on the Top of Stack, which the stack pointer currently points to - sometimes called TOS.  For historical reasons of operational convenience, stacks often originate in high-memory and grow downwards. The two operations that access the stack are called PUSH and POP.  

You PUSH data (from the accumulator) onto the stack by first  decrementing the stack pointer so that it points to the new Top of Stack (the next free location) and then you store the data.  When you POP an item off the stack and load it back to the accumulator,  you increment the stack pointer so that it points to the new item which is the Top of Stack. This process is sometimes referred to as Post Increment and Pre Decrement. No data is overwritten or moved, just the value in the stack pointer changes.

To help automate the stack operations, it is convenient to have an addressing mode that has an auto increment or auto decrement indirect mode.

The table above conveniently summarises the Addressing Modes available on the MSP430 processor.  Most of these should be achievable on the Suite-16 design.