A New Year - and 2020 Vision.

A project log for Suite-16

Suite-16 is a 16-bit cpu built entirely from TTL. It is a personal exploration of how hardware and software interact.

monsonitemonsonite 01/13/2020 at 16:202 Comments

In mid-November, I traveled out to Northern California, to attend Forth Day at Stanford University - and to meet one of my Computing Heroes, Charles H. Moore - the inventor of Forth. Returning in late November, I got stuck in a bit of a rut, plus a lot of other things were putting pressure on my free time - which meant that the Suite-16 project was put on the back-burner with no further progress. My project-colleague, Frank, is currently touring Australia and Tasmania for the duration of January, and so that gives me a two-week  window of opportunity to take stock of the project so far and plan out the goals for 2020.

It was always my intention that Suite-16 would exist as a C-simulator, a computer implemented in standard TTL and as a verilog implementation to run on an FPGA as a soft-cpu.  In discussions with Frank, we have decided that now we have a working simulator, the next step is to convert this into a soft-cpu developed and running on opensource FPGA hardware. When this task is done, I will have had a lot more experience writing in verilog, and Frank and I, will have stable target hardware platforms with which we can do real system development.  The TTL processor will follow on later, as it will be a lot of hard work, but at least the architecture will have been thoroughly explored and documented by that time.

The FPGA family I have chosen to use is the Lattice ICE 40 series.  I first encountered these in early 2015 when Clifford Wolf announced his "Project IceStorm"  reverse engineered, opensource FPGA toolchain - allowing the Lattice parts to be programmed using a manageable, open source toolchain.  One of the first soft-cpus to benefit from this announcement was James Bowman's J1 Forth CPU. Video here:  James had previously used Xilinx parts for earlier implementations of his J1, but by May 2015 had proven that it would easily fit onto a ICE 40 HX1K - which is a 1K lUT FPGA used on the $25 Lattice IceStick development board. James and I have collaborated on a couple of projects, having first met at the Open Hardware Summit in New York in September 2011. 

In May 2016 a friend, Alan Wood,  and I decided to develop an opensource FPGA dev-board based on the Lattice ICE40 HX4K.  The result was the myStorm BlackIce, which is now into it's fifth generation. Hardware development took about 14 weeks from idea to the first 250 boards arriving from the manufacturers in Shenzhen, China. We debuted at  the 2016 OSHCamp (Open Source Hardware Camp) held annually in Hebden Bridge, West Yorkshire, UK.

In November 2016, I met up with James again at  Forth Day in Palo Alto, where he had implemented his J1 cpu on one of our BlackIce boards, and was serving his presentation as a series of jpgs from it.  The BlackIce hardware had been fully exercised and proven robust and reliable - and makes an ideal platform for soft cpus or SoCs.

The 2nd generation BlackIce II board has a Lattice ICE 40 HX4K FPGA and 256K words of 16-bit, 10nS SRAM.  Programming (configuration) is done over a USB connection, using an STM32L433 ARM Cortex M4 to act as the programming interface.  We could have just used a FTDI FT2232H as a USB to SPI converter (like everyone else does) - but frankly at $3.50 the FTDI device is too expensive and the STM32 offers so much more flexibility for less money.  Once the FPGA is programmed, the STM32 can be used to provide slave peripherals for the FPGA (such as ADC, DAC, UART, I2C, SPI etc).   Later generation of myStorm boards have all adopted this ARM/FPGA symbiosis.

Implementing a soft-cpu in verilog

verilog, like vhdl is a popular hardware description language or HDL.  verilog has its roots in C, whilst vhdl arose out of the US department of defense and is structured like Ada.  Both are equally used, but verilog has my vote, because I know nothing about vhdl syntax.

When James Bowman transcribed his J1 cpu to verilog, he implemented it as a very neat switch-case (casez) statement in fewer than 110 lines of verilog in his J1 Github repository.

Using James's code as a useful tutorial example, it's fairly easy to see how an instruction set implemented as a switch-case statement in C, translates cleanly to verilog. His code is well commented and easily readable, nobody likes obfuscated code (apart from obfuscated code masochists).

This code is just the cpu, and the interface to memory implemented in internal BRAM.  In a practical working system we will also require a module of code to define a serial communications UART,  an external SRAM interface and if we are feeling adventurous, a VGA colour graphics interface and external frame buffer. For a complete system a PS/2 keyboard interface would also be useful - and this can be added as a PMOD - external hardware module.


monsonite wrote 01/13/2020 at 22:59 point

Hi Ken - just getting started again on Suite-16 after a 6 week recess. This log was really just to help me gather my thoughts after a long break. BlackIce was a project I did with a friend back in 2016, but my day job got in the way.  Hoping to get my teeth into some verilog this week and implement Suite-16 over the next 3 weeks or so. Thanks for your continuing interest.

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Ken Yap wrote 01/13/2020 at 22:40 point

Thanks for the info on Blackice. I shall certainly consider it when I want to experiment with FPGAs.

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