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Improved Address Registers

A project log for Nits Processor

8-bit TTL technology processor

CedCed 01/20/2020 at 15:280 Comments

Our current CPU has many limitations, including on the register level. This post will look at how to improve the registers that handle memory or output addresses.

First, let's look at the current register capabilities:

So lets try to design a single General Purpose Address Register (GPAR) that would provide:

Now what type of instruction these registers should be able to handle :

This shows that at any given time, it must be possible to output any of the content of any part of the register ***AND*** input any other part of any other register. 

Possibly even within the same register:

We therefore need to separate the output action functions from the input action functions.

For output and reset:

For input and other:

In the end we need:

With a total of 10 bits, we can perform any type of function on the General Purpose Address Registers.

Here is the naming convention for the register select bits:

Here is the convention for the output action (all are asynchronous):

Here is the convention for the input/other functions (all are on the clock rising edge):

Lets now review what the 10 bits would be for the instructions listed above:

So what do we need to build such a register ?

This can be built using 2 types of ICs:

As usual, LED bargraph will be used to display the current value of the counter. We will be be using 470ohm current limiting resistors to reduce the power consumption if the register.

Finaly, there is a need for decoding the actions signals:

Note that 4 actions need to be synchronized with the clock.

More to come soon on this topic.

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