In the last log I complained how the 1 Hz square wave was glitchy and making the clock run fast. I thought about it and realised I had not checked the fan out of the CD4060 2 Hz output feeding the 7450 multiplexer. Turns out that the CD4060 is only rated for a 2 LS gate fan out. Unfortunately the 7450 I used is standard TTL, so effectively 4 LS loads or 1.6 mA. This was causing logic low to be too high and making the gate levels marginal.
I don't want to rework this board, at least not now, so I added a 4k7 pull down resistor at that gate (pin 1 of the 7450) to assist with logic 0. Now the signal is stable. In the remaining boards I'll be using a 74LS50 which will be fine. I'm running out of old standard TTL chips anyway.
I would have caught this issue at the breadboarding stage, except that I didn't test the combination of the CMOS output with TTL input due to the issue of the 32.768 kHz crystal not oscillating on a breadboard which I have previously blogged.
Lessons for me: When mixing logic families, check the logic levels and loading limits, and the breadboard should test as much of the real operating circumstances as possible.
Declaring this project completed. I may write a page or two when I find a good presentation for making gifts. I'm considering mounting the board in a wooden photo frame that sits on a desktop.