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FPGA debugging

A project log for CyL3D

Rethinking POV : what about 3D?

AlexisAlexis 06/13/2021 at 18:170 Comments

By Ambroise:

We are using the PIO core IP from Intel to implement debug registers accessible from the HPS to communicate easily with the FPGA. After testing that we could read and write such a register, I implemented a shell accessible in a Linux terminal inspired from ChibiOS.

I used those IPs to act as bypass registers in our FPGA modules. The implementation is still ongoing, but I currently have a shell command to test the correct soldering of the LEDs (by lighting all of them in a dim white).

The next step will be to complete all of our FPGA modules as well as their basic bypass register and test-benches (should be done by Monday).

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