So when I started the design I had started with a 16-bit wide memory. After looking a little more closely at the cartridge spec I realize there was not enough IO for 16-bit and barely enough for 8-bit so I changed gears and decided to target an 8-bit part instead. However, I continued to use a schematic symbol for a 16-bit part and just assumed that it would only use the lower half of the pins. My assumption was incorrect and actually between the two variants it roughly uses every other data pin. It also uses the other DQM pin.
Luckily half of the data pins only required remapping on the FPGA side and all the other incorrect pins went to NCs on the chip. All that was necessary was to add bodge wires to connect the right pins in.
When it came time to use it, it just worked. SDR RAM is pretty forgiving and I don’t think we were clocking it anywhere near it’s limit.