NXP describes the PN7150 as a high-performance version of the PN7120, which is a plug’n play NFC solution for easy integration into any OS environment, reducing Bill of Material (BOM) size and cost compared to say the pin compatible PN532 controller. It provides direct connection to the main host (MCU or MPU) by I2C-bus and the NCI 1.0 communication protocol.
Like the older PN7120, the PN7150 has an embedded Arm® Cortex®-M0 microcontroller core, which is loaded with integrated firmware, supporting all NFC Forum modes for contactless communication at 13.56 MHz. This simplifies application development and implementation as all the NFC real-time constraints, protocols and the device discovery (polling loop) are processed internally.
The PN7150 embeds a new RF contactless front-end supporting various transmission modes according to NFCIP-1 and NFCIP-2, ISO/IEC 14443, ISO/IEC 15693, MIFARE Classic IC-based card and FeliCa card specifications.
The NXP Single Board Computer (SBC) Demo Kits
NXP have 3 configurations of it's PN7150 NFC Controller SBC kit:
- OM5578/PN7150ARD for Arduino R3 boards
- OM5578/PN7150RPI for Raspberry Pi
- OM5578/PN7150BBB for BeagleBone Black/Green/Blue
Another useful PN7150 reference design is the Mikroe NFC USB DONGLE. However, the antenna on the Dongle is a much smaller size and so the matching circuit used is different.
For the purpose of this project, the OM5578 Interface Board, which sits on top of the SBC kit, will be used as the reference design as the antenna shape and size conveniantly fits within a FeatherWing Tripler protoboard.
Besides the data sheet and the user manual, NXP provide two very useful application notes, which help guide the design elements:
- AN11756: PN7150 Hardware Design Guide
- AN11755: PN7150 Antenna Design and Matching Guide
OM5578 Hardware Design Review
PN7150 Host Interface
There are 4 possible I2C slave addresses for the PN7150. These are set as follows:
|I2C Address (R/W)||I2CADR0 (pin1)||I2CADR1 (pin3)|
|0x50/0x51||0 (GND)||0 (GND)|
|0x52/0x53||1 (VDD_PAD)||0 (GND)|
|0x54/0x55||0 (GND)||1 (VDD_PAD)|
|0x56/0x57||1 (VDD_PAD)||1 (VDD_PAD)|
I2C Pullup Resistors are required. These were not included on the OM5578 interface board, so these will be be added into this design. The values of these resistors can be determined using NXP's I2C bus specification and user manual (UM10204).
For this design, 4k7 resistors were chosen on the assumption that Standard-mode (100k) is used as default. As the circuit if pretty compact, one could assume that the bus capacitance is below 100pF for Fast-mode (400k) to work too.
The hardware design document (AN11756) recommends that the IRQ pin is connected as an external interrupt to the host controller. The PN7150 IRQ signal can be configured active high or active low via the NCI Configuration API. This configuration is stored in non-volatile memory. The IRQ signal will be active any time data is available in the PN7150 send buffer. The IRQ pad state is maintained during the standby mode and is configured as pull down in hard power down mode.
The VEN pin is used to reset or activate the PN7150 chip. When VEN is greater than 1.1V the PN7150 chip is powered from VBAT. When the VEN pin is pulled lower than 0.4V, the PN7150 is in a hard powered down state. The chip is reset when VEN is switched back to a voltage level higher than 1.1V.
PN7150 Clock Interface
The 13.56MHz RF field carrier accuracy requirements are not compatible with the use of an internal oscillator, which can be found within the PN7150 ARM Cortex M0+. An external 27.12MHz crystal needs to be used as the input clock for PN7150, which is attached to the XTAL pins.
The following crystal oscillator have been properly checked by NXP as suitable for use:...Read more »