Solar Charger & Balancer for Lead Acid Stacks

Charger & Bidirectional Balancer for 48V Lead Acid Battery Stack

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With a working framework for MPPT, I've started working on the design for a more capable PV charger for a 48V lead-acid battery stack. The charger not only has to charge the stack but also maintain charge balance across the individual batteries. Keeping the batteries balanced in the stack is important for maximum run-time and service life. Unfortunately there aren't many options for charge controller chips because most of the focus is on lithium batteries.

The basic charging function operates on the stack.  Moving charge between between individual batteries is more challenging so I've focused on this area of the design first.  To maximize the stack's performance, the balancer must be capable of moving charge to or from any combination of batteries simoultaneously.  And, it must be able to monitor the individual battery voltages to assess charge state.  All of this requires working around the common mode voltage of the stack.

Here's the conceptual schematic for the balancer section.  It depicts a stack of four 12-volt lead-acid batteries but could be extended to taller stacks.  

It uses bidirectional isolated flyback transformers operating at 100kHz to transfer charge and to sense battery voltage.  The flybacks form an isolation barrier between the stack and what I call the balance bus (BBUS).  The BBUS also contains a 12V lead-acid battery (but much smaller than those in the stack, say 9Ah) that powers the controller and serves as a resevoir for charge exchange.

One quarter of the flyback control & sense circuitry is depicted.  The secondary is connected to a battery in the stack.  The drive circuit is comprised of pulse transformer T1, current sense op-amp U2, and gate driver U3.  U2 & U3 function as a Set-Reset latch to maintain a constant on-time of ~ 5uS.  The controller's drive pulse of 1uS is transfered across the isolation barrier via T1.  U3's gate drive output goes high, Q5 turns on, and L1 begins to charge.  Positive feedback to U3's input via D6 maintains the gate drive.  As L1 charges the voltage across R15 rises.  When it exceeds the voltage set by R18 & R19, U2's output goes high and turns on Q6.  The gate drive turns off and the duty cycle terminates.  L1 discharges to the battery bus.

The circuitry looks complicated but is really quite simple.  It's comprised of a few SOT-123/143 chips and a handful of capacitors & resistors.  It operates on the battery's voltage; no regulation is required.  Constant on-time is maintained regardless of battery voltage because limits are ratiometric:  as the battery voltage varies so does the reference voltage at U2's inverting input.  L1's current ramp also changes in proportion to the battery voltage.

I chose this approach because it avoids the need for a microcontroller with firmware, regulated power supplies, and a potentially more sophisticated & expensive communication scheme across the isolation barrier.  I also want to be able to centrally control the drive timing for lower EMI:  letting the drives operate asynchronously, even at the same frequency, may increase resonant harmonics.

Of course such a simple scheme eliminates direct measurement of battery voltage.  The solution is inspired from a Linear Technology application note (AN112) written by Jim Williams & Mark Thoren back in 2007.  In it they describe the use of a pulse transformer to measure cell voltages in a stack.  A flyback can also be used for this.

To measure the voltage of a battery in the stack, the controller issues a drive pulse to the secondary.  During the on time, the voltage imposed on the negative node of L1's primary (Drain of Q3) will be the sum of the voltages of BBUS plus BT2 (minus transformer error and current sense resistor R15 voltage drop).  If this voltage can be sampled at the mid-point of the duty cycle then the battery's voltage can be calculated by subtracting BBUS & measurement offset and applying a correction coefficient.

R11 & R9 scale the voltage at Q3's drain and U1A buffers it to eliminate error due to the relatively low impedance created by R4 & R6.  U1B is a unity gain differential amplifier that subtracts BBUS from the measurement.  U1B's output is sampled by the MCU's ADC, the value is scaled and a correction coefficient applied to derive the battery...

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Final LTspice model used to validate the prototype 200713.

plain - 7.25 kB - 09/01/2020 at 16:41


SEPIC prototype PCB project in Kicad.

Zip Archive - 401.56 kB - 08/29/2020 at 03:45


SEPIC prototype firmware.

Zip Archive - 486.77 kB - 08/29/2020 at 03:44



SEPIC prototype design workbook.

sheet - 94.38 kB - 08/29/2020 at 03:42



Titan analysis of coupled inductor design for 150kHz prototype evaluation.

Adobe Portable Document Format - 66.66 kB - 07/13/2020 at 23:07


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  • Evaluating the SEPIC Prototype

    Brian Cornell08/29/2020 at 05:00 0 comments

    Okay, I finally got this thing built and completed a preliminary evaluation. The Kicad, MPLAB projects, and updated design workbook are posted in the files section but don't rush to build it.


    • Input voltage: 10 - 80 volts
    • Input current: nominal 4.3A @ 62V, full power
    • Output voltage: 56V
    • Output current: 4.5A (max)
    • Maximum continuous power @ V_in > 60V: 250W
    • Maximum continuous power @ V_in 10V: 45W
    • Control mode: average current
    • Bias supply: 12V
    • Operating temperature: -20 - +50C (not validated)
    • Design efficiency: 93%

    Note that the power derates as the input voltage declines. This keeps the input current relatively constant and tracks with the maximum power available from the PV panels. Initial efficiency was closer to 90% but after improvements to the output diode, D2, it achieved 92% efficiency at 250W.

    Overall, it worked as designed. The control loop is stable thru all operating regimes (with both external & internal ramps) and the coupled inductor / ripple current steering is solid. The coupling capacitor, C_ac, and associated snubber performed as expected with no resonance and within expected operating limits.

    It does have some problems that are mostly the result of inattention because of my hyper-focus on SEPIC specific aspects of the design. The layout is also sub-optimal with several 'loop' jumpers to accommodate current probes at the expense of increased inductive parasitics.

    Switch snubber. The most serious is switch Q2 and its snubber. The root problem is the ring at turn-off. CH1=D-S volts, CH2=current sense (CT) circuit output, CH3=L1 primary current, CH4=L1 'secondary' (coupled) current.

    The snubber does not fully dampen it but is still absorbing 3+W more than anticpated (for total ~ 4.5W). That, combined with inadequate Cu area on the PCB, sends the snubber resistor north of 200C in 30 seconds at full power. Since a proper fix would be difficult, and this wasn't the focus of the build, I decided not to fix and worked around (limited high-power run-times, forced-air cooling) during the evaluation. 

    Amazingly, Q2 did not avalanche/fail and ran close to predicted temperature. In an attempt to measure the non-dampened ring, I did remove the snubber but that resulted in the switch's immediate failure. The revised design will use a non-dissipative snubber that will probably send the recovered energy to the bias supply. To ensure robustness the revised design will use a different MOSFET with a higher D-S rating.

    Output diode. The output diode, D2, had similar problems at the anode during turn-off because I hadn't included a snubber for it. CH1=voltage at anode referenced to ground, CH3=voltage at cathode referenced to ground, CH4=diode current, M1=CH3+CH1 (incorrect).

    Its reverse voltage rating (200V) was being exceeded and it was avalanching - resulting in ~ 5W of additional losses (incredibly, albeit a Schottky, it did't fail). I fashioned an RC snubber which eliminated the ring except for the initial negative inductive swing but the high losses continued. I replaced the schottky with a 400V fast recovery diode (but higher forward voltage) and netted 4W. Interestingly, there is still a 10A excursion during recovery. M1 correctly shows the voltage across the diode and it is well within its V_r (CH3-CH1).

    External slope. The external slope compensation circuit worked well but I made the mistake of powering it with Vdd (+5V) instead of Vcc (+12V). The problem with a 5V supply is that the slope becomes asymptotic above ~ 4.5V. Hacking the PCB to reconnect to Vcc and adjusting R1 for a ~ 1V/uS fixed the problem.

    The external slope does have a ~ 500nS non-linear region at the start of the duty cycle due to propagation delays in the constant current source but this did not induce control problems at no/light-load conditions.

    Current sense switching spikes. During initial evaluation the over-current protection would engage when loading at 250W with input voltages < 60V. A review of the...

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  • Completing the SEPIC Prototype Design

    Brian Cornell07/13/2020 at 23:21 0 comments

    I ended my last post with mention of the snubber for C_ac to dampen the resonance with L_l. And, analysis & design of the control loop wasn't done. Completing the design resulted in further modifications and some corrections. An updated design workbook is posted along with a more complete LTspice model. This post addresses five areas:

    • Current mode control and slope compensation
    • Implementing leakage inductance
    • Snubber for C_ac & L_l resonance
    • C_ac AC ripple voltage ratings
    • Control loop design

    Current mode control and slope compensation. Current mode controls peak inductor current; not average and therefore requires slope compensation to prevent subharmonic instabilities. With a PIC MCU the ideal method is to use the Programmable Ramp Generator (PRG) to apply a negative ramp (M) that subtracts from the outer (voltage control) loop error amp signal. This compensated signal is compared to the switch current sense signal to control on-time. The diagram below depicts the peripheral configuration.

    I prefer the use of current transformers whenever possible. They are efficient and require almost no conditioning to provide a clean sense signal. Their major limitations are space and reset time (volts-seconds product).

    The value of M is in A/uS but uses the voltage analog of the current sense circuit. So with a sense of 400mv/A and a required M of 0.5A/uS the PRG's ramp would be 200mv/uS. Hence, the design of the sense circuit not only effects the power stage gain but also slope compensation. Other considerations:

    • The PRG's minimum ramp is 200mV/uS: the derived M slope must be >=.
    • The resolution (e.g. volts per amp) of the current sense circuit: a smaller V/A provides more dynamic range but a lower M value.
    • Inductance: a lower L increases the charge/discharge slopes (M1/M2) but can exceed current sense circuit head room.
    • CT reset voltage: a function of the volts-seconds product that is effected by the maximum current the CT must measure, on-time, and the V/A value derived from the burden resistor.
    • Switching frequency: higher F_s reduces L and increases M at the expense of increased dissipation.
    • Input ripple current allowance: setting a higher value reduces L and increaes M but will impact the CT design
    • Changes to L or F_s effect the value of C_ac, the induced AC ripple, and L_l requirements of the inductor.

    At an F_s of 100kHz I could not achieve an M of 200mV/uS without excessively high input ripple or loss of needed dynamic range in the sense circuit. 200kHz would have been perfect but the switching losses became excessive. 150kHz provided a workable compromise - just barely. So, I plan to include an alternate external positive ramp circuit that allows for smaller than 200mV/uS. For the prototype it can coexist on the PIC without conflict. The downside to this option is additional components and pin consumption. A small ramp can also be problematic due to a smaller S/N ratio that results in jitter in the output.

    Implementing leakage inductance. Adding leakage inductance to the coupled inductor is highly dependent on the selected core, bobbin, winding placement, and methods. I have opted for a gapped RM core with a conventional bobbin (e.g. single winding area - not split, etc.) for size and availability from a mainstream supplier. This, along with winding by hand, limits the amount of leakage inductance obtainable: basically how many layers of tape you can place between the windings before running out of window area.

    The higher operating frequency allowed for the use of an RM12 (vs. 14 for 100kHz). Testing of several builds showed that ~ 6uH of leakage was the limit (using the outer winding as 'primary' or L1 from the spice schematic). Interestingly, the outer winding always (across different test builds) measured several uH more (inductance) than the inner. I hypothesize this is due to the larger MLT and closer proximity to the core's outer legs which are not gapped.

    An alternate way to implement L_l is as a physically separate inductor...

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  • SEPIC Design

    Brian Cornell03/09/2020 at 01:28 0 comments

    Being my first SEPIC design, I invested a lot of time reading up on their theory and design.  Unlike the more mainstream topologies information is a bit fragmented, so it took a while to assemble what I considered a thorough design model.  What I share here is a qualitative discussion that is by no means complete:  I found it hard to succinctly describe the component relationships and key design considerations.  The supporting mathematical (design) model can be found in the accompanying workbook.

    The Limitations of the SEPIC.  A machine doesn't need a lot of parts to be complicated, and SMPS demonstrate this well.  Worse, a small component count simply means that each one possesses several critical parameters and that changing one cascades thru the entire design.  And so it is for the SEPIC:  the coupling capacitor and coupled inductor dictate the design.

    The SEPIC shines for its ability to transparently boost or buck the output voltage while maintaining a constant input current (with a ripple component).  It performs best when the input voltage varies about the output by a range dictated by the current and voltage stresses imposed on the circuit elements.

    The prototype for this project is spec'd to deliver 250W at 56V with an input of 63V.  At 93% efficiency the input current is 4.3A.  Skipping the math, the coupled inductor will see over 9A peak since each winding will carry over 4.3A.  Add a 20% saturation margin and the inductor's saturation rating must be at least 10.8A.  The coupling capacitor's RMS [ripple] current ratting, which is approximately equal to the input current, must be at least 4.3A.  These are large values but not unrealistic.

    But if this design is expected to deliver 250W with a 10V input, the inductor's saturation current rating would be 47A and the capacitor would require an RMS rating of 28A.  Completely untenable.

    The variable impedance of a PV system extends the operating regime of the SEPIC into this crazy territory since full power is only attainable at MPP.  At 10V with the selected panel about 90W is available, but the supply will only need to deliver 45W (because the final design will interleave two supplies).  This keeps the input current relatively constant at ~ 4.9A.  Above MPP the current drops rapidly to zero so the design isn't much concerned about operation at higher voltages except tolerating the panel's open circuit voltage under no-load conditions.

    The Coupling Capacitor.  The coupling capacitor facilitates the unique boost/buck property of the converter.  This is because L1 is isolated from the output making duty cycle the sole determinant of output voltage just like the buck/boost topology.  But it is also its Achilles heel.  Half of the energy delivered to the output flows thru it.  This rectangular current waveform creates a high RMS ripple current thru C_ac.  Depending on the operating voltages and value selected for C_ac, the ripple voltage adds additional stress.  All of this imposes limitations on the type of capacitor that can be used and directly effects cost, size, and reliability.

    A small C_ac value requires less board space and generally costs less, but lower values have higher AC ripple and as will be shown later can effect the inductor design and EMI footprint.  The polarity across C_ac can also reverse when small values are used, and occurs when the ripple component exceeds the input voltage at maximum load.  Non-polarized types are most often used, but polarized variants may be a better choice in higher voltage & ripple current applications.

    SEPICs operating at higher voltages and RMS currents limit the type of capacitor that may be used and will likely increase the size & cost of the design.  In low voltage designs MLCCs are the obvious choice because of the large capacitance available in small, cheap, low-inductance...

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  • SR Latch rev 2

    Brian Cornell01/15/2020 at 22:25 0 comments

    I finally got around to testing with the TI TLV1805 comparator.  Basically the same circuit but I did rework the PCB for a tighter layout.

    The TLV1805's performance was disappointing.  It's propagation delays were about the same as the MIC6270 - about 1uS.  Aside from a cleaner (square) output due to the push-pull driver, its performance (ratiometric, stability, etc.) was identical to the MIC.

    I decided to lower the Vref to 110mV which equates to 3.3uS, so with a 1uS delay I'd get a duty cycle under 4.5uS.  I needed to make sure the timing would track linearly to the reference since going much lower becomes a problem for stability in noisy environments.  The duty cycle dropped to just under 4.5uS - okay but not much margin if the design dictates a shorter on-time.  Below is the timing trace - note the cursors marking Vref and turn-off time.

    This outcome forced a reevaluation of the MIC version: I updated Vref to 110mV and repeated the timing tests.  It bested the TLV by nearly 400nS for a duty cycle just over 4uS:

    CH1=gate drive input, CH2=gate drive output, CH3=current sense input @ comparator, CH4=comparator output.  Aside from the TLV's clean output pulse (hard to see), the traces are identical sans the shorter DC of the MIC.

    The MIC's output has more slew because of the open-collector output stage and pull-up resistor but it does not effect performance.  Given this, the MIC6270 is the obvious choice.  The only points against it are the need for a pull-up resistor and temperature qualification to ambients of 85C (vs. 150C for the TLV).  Temperature should be okay since thermal management will keep the maximum rise under 30C with a maximum ambient of 40C.  So, with a unit costs on Digikey of $0.33 plus a $0.10 resistor I can buy two of these for less than the unit cost of a TLV1805.  Sometimes the cheaper part really is the better choice.

    While I was wise to test both versions, I could have been smarter and known  the TLV1805's performance if I had studied the data sheet more closely - as it applies to this application.  In this case it is the combination of hysteresis and overdrive.  The TLV has 14mV of hysteresis intentionally built-in to prevent false triggering.  Assuming Vref is centered in the hysteresis, 7mV equates 200nS:

        Given (V * dt) / L = di

        and I * R = V, the current sense voltage increase by

        ((V * dt) / L) * R,

        substituting ((14 * 200e-9) / 8.35e-6) * 0.02) = 6.7mV

    Figure 47 shows the propagation times based on the overdrive (the instantaneous difference between the comparator's inputs) with a 12V supply.  At 25C it's ~ 800nS.  This plus the hysteresis time delay is about 1uS.

    Conversely, the MIC6270 does not have the hysteresis feature and its propagation times are solely based on overdrive.  A 20mV overdrive will produce a 5V high output in about 500nS which is close to observed performance.

    Okay, the MIC it is.  Now I can start work on a complete draft of the balancer section and prototyping the SEPIC for the charger.


    Brian Cornell01/06/2020 at 02:16 0 comments

    In between work on the balancer I've been considering topologies for the charger.  So much depends on the panel configuration and working voltage.  Within the charger, higher voltages correlate with higher efficiencies because of lower currents.  This is even more important with a homebrew design where heavy-weight PCB costs are prohibitive and inductor / transformer fabrication capabilities are limited.

    The TS350 project provided many lessons on the limits of power, efficiency, and transformer design with low input voltages that I want to avoid repeating.  I settled on 500 watts with a nominal 60-65V input.  Two 270W, 31.4V, panels in series would power the charger and deliver 540W at peak MPP.  Of course these are perfect condition numbers that will [likely] never be obtained.  Further, it requires the charger to have a minimum 92.6% efficiency (500/540).  With an input current of 8.6 amps RMS this could prove challenging.

    Here's the I-V curve for the panel I'm considering.  A lot of energy is left on the table if the charger isn't able to boost the panel voltage to that of the stack.

    Even at 10 volts there's better than 90W available.  With two panels in series there will be 180W @ 20V.  So I need a topology that can handle open circuit voltages in excess of 80V and capable of boost to at least 20V and preferably 10V.

    Another key criteria I have is to minimize input current ripple since the panels will probably be located several meters away from the charger and high frequency ripple generates copious EMI and increased losses in the supply wiring.  For example, a pair of 10AWG wire ten meters in length with 3mm lead spacing has ~ 3.36uH of inductance.  To limit the voltage noise to 50mV with a ripple current of 1A would require 5,400uF of bulk capacitance.  Output current ripple isn't as much of a concern since the charger will be located close to the battery stack and they are essentially a very large super capacitor.

    Last, I prefer the power stage to be as simple as possible:  defined by a minimum of switching and inductive elements since these incur most of the efficiency loss.

    So far the design criteria are:
    • Output voltage=56V
    • Output power=500W
    • Output current=9A
    • Efficiency=92.6%
    • Nominal input voltage=63V
    • Maximum input voltage=90V
    • Minimum input voltage=10V
    • Maximum input current=10A RMS
    • Input current ripple <200mA RMS
    • Simplified power section
    • Isolated output not required (the battery system must be on earth ground with the panels)

    As a rule I try to avoid center-tap windings on transformers.  First, they are inefficient:  each half winding is only active for a half cycle.  Second, they waste valuable winding area and, depending on the number of turns & windings, can require a larger core size than non-CT variants.  Third, the parasitic winding capacitance leads to damaging ringing on higher voltage windings:  the end-end voltage is 2x the voltage applied to the half winding.  This is worse for windings with a large volts-per-turn ratio.  Eliminating #3 requires equipment & skills that I don't possess.

    Against that backdrop I considered traditional full & half-bridge topologies.  They would probably work but either require center-tap transformers or full-bridge switching.  The secondary voltages aren't particularly high, but the voltage difference from end-end of the secondary will be 120V and that is close to the threshold I have found for excessive ringing on my home-built transformers.  Conversely, a full-bridge rectifier on a conventional secondary creates a lot of loss.

    Then there are flybacks.  A non-isolated flyback won't work because it can't regulate to a lower voltage.  An Isolated flyback can, but even in continuous mode they generate significant input switching ripple because the input current is discontinuous.

    That sent me looking for something new.  I stumbled on this current-fed...

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  • SR Latch rev 1

    Brian Cornell12/30/2019 at 22:13 0 comments

    The pin pitch on the SOT-23 packages is too fine for my homebrew PCB abilities so I had it fabbed by Oshpark.  It was also a good practice for using Kicad instead of Eagle.

    Glad I did since Captain Obvious made the mistake of trying to use the OPA197 as a comparator.  I did so for reduced component mix and because comparators with wide voltage supply ranges have have long propagation delays - greater than 1uS.  But as anyone who knows op-amps will tell you they cannot be used as high-speed comparators, no matter how fast they are (GBW).  With a large voltage delta, the inputs saturate and take several microseconds to desaturate.  I measured propagation delays greater than five - totally unusable.

    I found two comparators that might work.  Microchip has a pin-compatible open-collector, wide supply range comparator (MIC6270) that's cheap but slow - on the order of 600nS-1.3uS.  But I could evaluate it in the existing prototype circuit.  TI has a push-pull (TLV1805) that costs the same as the OPA197 and is much faster - 400-600nS - but isn't pin compatible.

    For both, the approach is to set a lower Vref to commence turn-off at a lower current which, when accounting for their propagation times over temperature, terminates the duty cycle appropriately.  This works for normal operation but won't protect against dead shorts.  However, this is an acceptable trade-off since the circuit will be fused and a short means something is broken anyway.

    I was able to evaluate the MIC6270 immediately with just the addition of a pull-up resistor to the existing PCB.  I did a new layout for the TI chip that's a bit more compact (and hopefully transferable to a complete design).  I'm already leaning towards the TI comparator since it's faster and has a push-pull output stage that eliminates the resistor.  I'll post a log when that evaluation is done.

    Here's the circuit that the OPA197 & MIC6270 were evaluated in.

    They were fitted to the flyback prototype and replaced the conventional gate drive circuit.  A 1uS drive pulse is issued by the PIC.

    It did a bit better than expected.  This trace was taken with a 14V supply emulating the battery.  CH1 is the drive pulse seen by the gate driver's input, CH2 is the gate drive output, CH3 is the MOSFET source pin (e.g. current ramp), and CH4 is the comparator's output.  At 14V the comparator should trigger at 140mV.  There's about 800nS of delay.

    Here's the same trace setup at 10.2V.  Identical timing (ratiometric) as intended.  Note the drop in the positive feedback as well as the droop at the end of the drive pulse.  Below this voltage the driver would fail to latch because the voltage divider (R6/7) minus D4's forward voltage was less than the pulse drive input.  The droop is due to the feedback loop's relatively high impedance.  So a refinement is to select divider values that ensure latching across the intended operating voltage with sufficient noise margin.  The bottom of the divider could be eliminated but the higher voltage adds time to the turn-off.

    I spent some time characterizing at various voltages, running in sampling mode (10kHz) as well as charge transfer (100kHz) and its operation is stable.  Voltage measurements are consistent with those taken using the standard gate drive.  In a pinch this circuit would work but I'm betting the TI will do better.

    Last, the gate driver and MOSFET are not matched; the MOSFET's gate charge is considerable since it's designed to switch 100A and I had to use a 10 ohm gate resistor to limit peak current for the driver.  Not surprisingly, the gate driver's output trace (CH2) shows a rounded turn-on/off and there is considerable ring with more dissipation from the MOSFET than expected.  Not a big deal since wasn't the focus of validation.

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