This is a re-creation of a Cosmac ELF computer, Coded in SpinalHDL.
The goal of this project is to end up with a cycle-accurate 1802 processor that can be used in FPGA designs easily.
When I start the project I was new to SpinalHDL but I had attempted in the past to write the same processor in VHDL. However, language complexity and the sheer amount of code and time needed to write and debug that project ended the work on it.
I have put a lot of the details about the project in the Github readme.
Today I finished writing and testing the CDP1861 Video Display Controller. It was a addon for the Cosmac ELF, and was also used in the Cosmac VIP, and the RCA Studio II game console. It has a resolution of 64x128, with software you can change it by redrawing lines which can give you 64x64, and 64x32.
I was able to simulate both the 1802 CPU and 1861 VDC. and also have the CPU running the driver software for the VDC that help a lot with finale testing.
But most of the testing was done while feeding in simulated signals.
The chip are pretty simple, It uses two counters, one for counting lines(Line Counter) and the other for counting machine cycles (MC Counter).
MC Counter is incremented by TPA(Rising Edge) and by TPB(Falling Edge) and holds a max count of 27 and overflows back to 0, which increments the Line Counter by 1.
There are 14 machine cycle per line, 8 of which are DMA, and the other 6 available for CPU to run instructions.
The Line Counter holds a max count of 262 and overflows back to 0. This gives a total of 524 lines, or 262 lines per NTSC field.
Base off the counters, states are generated for the CPU flags Interrupt, DMA Out, and EFX. Along with the V Sync and H Sync signals, that get XOR together to make up the Comp Sync.
The VDC relies on the CPU being in the right cycle when it starts the DMA transfer. If the state is not correct it will hold the MC Counter for one machine cycle, allowing the VDC to sync with the CPU.
A shift register is user to shift out each pixel at a clock frequency of 1.764Mhz. it's also inverted from the same clock used by the CPU.
Disp Off and Disp On allow for disabling and enabling the Interrupt, DMA Out, and EFX flags.
This is a picture of the video output from the 1861 VDC running on my FPGA, using the classic test program that was apart of the article on adding it to the Cosmac Elf in the Popular Electronics magazine. You can also see a video of the output on my instagram