The project was completed in stages. In the first stage, I stuffed the PoE and power supply components on the power / logic board and verified the power supplies supplied 25 volts for the tube anodes and segments and 3.3 volts for the logic and microcontroller. The 25 volts is supplied from a 24 volt DC/DC converter but I used its adjustment pin to crank the voltage up to 25

After testing the power supplies, I stuffed the components on the tube board. The tube board contains its own 1.5 volt and 5 volt supplies. The 1.5 volt supply powers the tube grids. The 5 volt supply powers the Microchip HV5812 high-voltage display drivers that switch the tube segments on and off. The communication between the power / logic board and the tube board is via a SPI interface running at 3.3 volts. Because the HV5812 drivers inputs are referenced to 5 volts, there's a 3.3 to 5 volt TI level translator IC on this board too. The tubes socket were constructed using 1 mm pin sockets soldered into 1.95 mm holes.

Here's a video of the tube board running before I had the power / logic board assembled:

In this video, the 25 volt power for the tube board comes from my Keysight bench power supply. The 3.3 volt power for the input side of the TI level translator and the SPI data is from a Particle Photon with software to update the data on the display over the Particle Cloud.

The next stage of the project was to finish stuffing the power / logic board and bring up the PIC18F67J60 microcontroller. Here's a video of the almost finished clock:

In this video, the clock is powered over Ethernet and the PIC has received an IP address using DHCP successfully. The digits spin while the DHCP process is completed. Once completed, the received IP address is scrolled across the digits.

Over the next few days, I finished the software to get the time from an NTP server in pool.ntp.org and display the time on the display. Once the software was done, I removed the debugger cable and finished assembling the enclosure.

The most worrisome part of this project was whether the Ethernet jack on the two circuit boards stacked up and hanging from slots in the side profiles of the enclosure would match up with the cut out for the Ethernet jack on the rear panel. It worked out perfectly on the first try.

Design files are posted at https://github.com/bikerglen/poe-vfd-clock