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7x9 LIFO using Verilog

Design and verification of a 7x9 LIFO using Verilog

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A 7 bit deep and 9 bit wide LIFO is designed and verified using Verilog. LIFO can be used as a stack.

design.sv

Verilog design file for 7x9 LIFO

x-svsrc - 773.00 bytes - 01/23/2020 at 06:53

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testbench.sv

Testbench for 7x9 LIFO

x-svsrc - 1004.00 bytes - 01/23/2020 at 06:53

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waveform_lifo.jpeg

Output waveform of 7x9 LIFO.

JPEG Image - 116.95 kB - 01/23/2020 at 06:51

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