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A project log for ReTest-yg

YG's own version of Mateng's ReTest, but with different features and a palindromic project number!

Yann Guidon / YGDESYann Guidon / YGDES 11/16/2019 at 19:490 Comments

(updated again)

Here it is !

The first plot of the Von/Voff of 90 RES64A relays, found on vseste's eBay store in Moldavia:

The range is extended because the relay is in series with 4×2K Ohm resistors, the ratio is about ×5. Add another ×100 ratio because I count in steps of 10mV. What matters is that ALL the parts are tested in the exact same conditions and we have a pretty good scatter pattern. I still have 60 parts to test and 110 should arrive in the coming weeks.

I have uploaded the script on the files section.


153 relays have been tested and the results are looking good. 1 relay was DOA and will be sacrificed during an autopsy.

I have uploaded the raw data as RES64.152ok.log and here are some early plots :

X-Y plot

gnuplot script:

set xtics 0.2
set ytics 0.2
set xr [0:5.5]
set yr [0:3.5]
set xlabel 'Von'
set ylabel 'Voff'
d(x)=x
plot "RES64.log" using ($2/500):($3/500) w points pt 7, d(x) notitle with lines linestyle 2

 I have traced the diagonal line because the distance from the point to the diagonal indicates the hysteresis.

There are two applications for the relays and they are in 2 zones of the dot cloud :

  1. Amplifier/buffer : this requires a low Von so it's the leftmost dots
  2. Latch/flip-flop : they require a large hysteresis so they are furthest from the diagonal line.

The "dots" will be allocated later when I have the whole stock but we can already see some of them used for specific purposes.

Hysteresis

gnuplot script:

set ytics 0.5
set xtics 10
set ylabel 'Hysteresis'
set xlabel 'Part sn#'
set yr [0:5]
set xr [0:153]
plot "RES64.log" using 1:(($2-$3)/500) w points pt 7

Apart from a few outliers, hysteresis is well between 1.5 and 3.5V.

Candidates for the buffers can be selected by first sorting the list by hysteresis, then sorting by Von.

Margin

gnuplot:

set xr [0:153]
set yr [0:6]
set ytics 0.2
set xtics 10
set xlabel 'Part sn#'
set ylabel 'V'
plot "RES64.log" using 1:($2/500) title "Von" w points pt 7, "RES64.log" using 1:($3/500) title "Voff" w points pt 7

Even with the occasional outliers, we see the other major benefit of reed relays : there is a much larger "gap" between the Von and Voff clouds, compared to the RES15. The larger the gap, the less sensitive to parasites ! There is at least 1V of margin so the power supply can be less filtered => cheaper and more reliable !

OTOH the "outliers" can be used as buffers.

Register set supply voltage

gnuplot:

set ytics 0.5
set xtics 10
set ylabel 'Hysteresis'
set xlabel 'Part sn#'
set yr [0:5]
set xr [0:153]
plot "RES64.log" using 1:(($2+$3)/1000) w points pt 7

The question of the voltage to apply to the register set is critical as well, since reliability/retention are affected, but easy to evaluate : it's simply the average of Von and Voff, and is shown to be in a band centered around 3.2V. This means I can reuse the rails of the Numitron-based display modules, using -3.3V-0V-+3.3V. Or a 6.6V unipolar supply. Neat.

The band's medium value and width will change once the "sensor" parts are taken out of the pool. Overall it's a great news because the comfortable margin (compared to the RES15-based R7) greatly simplifies the design of the power supply. Not only has the current dropped (thus reducing the size of the filtering capacitors as well as the self-heating-related drifts) but there can be only one regulator and tuning point (instead of one per board). And because the load is constant, the working point is set with a simple rheostat in series, of a lower rating than what was planned for the previous version that used RES15s.


The register set will use a pair of relays for each bit and the first plot (XY) will help select the pairs : they are closest from each other. Maybe I can come up with some sort of automatic partitioning...

"Matching" relays further increases the resilience : when the power supply fluctuates, both relays will behave almost identically and this will prevent one bit from flipping while the other half didn't change.
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