The RPI is not a true real-time system, unlike a common microcontroller.

How do I evenly sample the inputs ? RPi SW can have some serious jitter (been there, done that...) but I have solved this for some years now, using the FIFO of the SPI port.

At a reasonable speed (in the 100K/1MBps range), the 16 bytes are enough to shield the system from interferences. JUST AVOID INTERLEAVING READS AND WRITES TO THE I/Os or the bus turnaround time will give you a penalty of 1/2µs.

In non-interruptible task mode, running as root, the kernel will interrupt the task once per second, which is well above the 5ms sampling time of a transition. Just don't forget to yield to the kernel after each sequence (nanosleep() ?) and you'll be safe.

How many data points do we actually need ? I believe 1K is the most that is required. Current is more important for binning with my logic topology. I can use a real computer screen to show the histogram (in framebuffer mode ?)

The other cool thing about the SPI port is the variable speed, which can be pretty finely tuned with the clock generator. But the UGLY secret of this port is the 9-bit scheduling, which inserts one dead bit cycle for every byte (I'm not kidding you, check with your scope !) so the actual sampling rate must be calculated carefully !

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(to be continued)