I felt that my method was not optimal but I was OK with it, by lack of a better system.

Then the HaD blog published this video :

The digits counter use a SCR-based circuit that uses one complementary pair per output.

It is very reminiscent of the Dekatron system, but with transistors instead of gas discharge tubes !

I have reproduced the circuit with Falstad's sim:

And here is the simulation. Don't mind the diodes to GND, they only help with preventing the sim to explode when the bias is too weird (no idea why).

That bias is a really, really surprising artefact that I had not seen before... yet. Its value is "somewhat" important, between maybe 8V and 11V. I'll have to investigate and it might explain why my previous SCR-based circuit failed.

It's genius because it simplifies my more convoluted circuit.

There is a big difference though : this pseudo-dekatron is synchronous to a fixed clock, and not self-timed. But this further simplifies my new idea because now, the RX is fully synchronous and shares a common input... The dekatron will steer the (buffered) input to one of the 8 latches, while also working as the state of a one-hot FSM.

The "pseudo-dekatron" (top row) receives the clock that lets a pulse propagate from the state 0 to state 9.

The buffered input data is latched by either one of the 8 transparent latches, one by one.

The output buffer is finally latched, all at once, when the whole word has been correctly loaded.

The cost : 2 (P+N) for the pseudo-dekatron bit, 3 per latch (2 FF+1write enable), so 8T/bit, 64+4 T for the whole datapath.

The Dekatron-like circuit is also great for the frequency predividers !