Sometimes, all you need to know is the right term to enquire Google.
So I was browsing here and there before I noticed that what I want to do is almost like a Dekatron, but where more than one element can be active at a time. Then I found Alan Yate's Dekatron Emulator.
It's nice though I haven't found yet how to coerce the chain to allow more than one bit set at the same time. But he muses thusly :
A micro-controller could clock different patterns into the ring and could control resetting it - reset logic is important for using as a real counter and would need to ensure the "0" cell fires alone on reset, in the practical circuit one cell will dominate on first power-up and clocking but it would need to be a formalised reset for counter use. With buffering the adjacent-cell problem could be removed and you'd have a bucket-brigade or delay line memory which might be useful for some applications.
Then it was obvious that the shift register I want to make is a delay line, or a bucket-brigade of capacitors, or a glorified CCD line. These are still pretty common in niche applications, such as sound delay lines but mostly they use MOS transistors.
Some more googling with the enhanced keywords ("capacitor bucket brigade shift register bipolar" is a mouthful that yields 1 260 000 result) and I find what I didn't hope to see, in the patent US3796928A filed in 1971. The prior art contains this schematic :
I don't see how this could be simpler. There are 2 transistors and 2 capacitors per "position" and the complexity is moved to a 4-phase driver. I also like that all the transistors are of the same type. However the retention time is quite low but this should be sufficient for a serial transmission. I'll have to find tricks for holding the value into buffers, which is also a very interesting problem for #Clockwork germanium.
This circuit would work nicely with modern (low-leakage) silicon transistors but a recent log (18. More characterisation) found that Germanium has a quite low breakdown voltage between base and emitter. This would limit the range to about 2V, otherwise the data could flow backwards...
I also hope that circuitjs will not explode during the simulations like it does when I use the SCR PNP-NPN topology...
A related (expired) patent filed in 1969 :
US3671771 : A charge amplifier for a bucket brigade capacitor store
And back in 1964 this strange circuit was filed :
And now I need a generator of non-overlapping pulses.
For discrete and leaky implementations, with old transistors and medium speed shifting, a mixed approach could work : 2 "basic" stages (2T+2C) followed by another T for buffering, like the above diagram. That's 3T per bit, and there might even be a way to select where the data would be sent (either the next bucket in the line, or the output buffer).