When selecting an ADC for a system application, professional industry-standards do not
recommend selecting an ADC at the EXACT resolution required for the application.
Approximation errors in ADCs are commonly due to Differential Nonlinearity
(DNL), Unipolar Gain Approximation, and Offset Error, all contributing to a loss of resolution and dynamic range. “For example, a 12-bit ADC with 4LSBs of integral nonlinearity error can give only 10 bits of accuracy at best (assuming the offset and gain errors have been calibrated). [SOURCE] ” The figure below illustrates a DNL error in an ADC design.

**NOTE** LSB stands for Least Significant Bit!

This ADC was designed for use with a 5kg load cell. Thus, a 12-bit ADC for this project will provide at minimum, 10-bits, if not more, resolution. The majority of the calculations used for the design of the ADC will consider an “ideal” 12-bit ADC. However, quantitative losses due to the aforementioned errors will be anticipated in the testing and results of the ADC. It is theorized that if 10-bits, of a 12-bit ADC are within mode of “reliable” operation, this allows for an approximate 12% error in tolerance of engineering acceptability.

Here, let's take n as our 12 bits of resolution!

What does this "bits per gram" value even represent?

Bits per gram is not a unit, you're right! This calculation merely indicates to us that for use with a 5kg analog load cell, we won't quite have a whole "bit" to represent 1 gram of measurement to use our whole range. In a perfect world, if an object weighed 1 gram, we'd have 1 bit of resolution to capture that information. Since we're not quite there, we can assume our accuracy is going to be off IF we intended to weigh 5kg objects; using our whole range. Instead, let's all agree to only weigh 4kg objects and leave that last whole 1kg as engineering tolerance!

Two Methods of Attacking ADC Approximation:

In this type of design, the ADC only achieves approximations (or “samples”) of an analog signal during an ascending count before resetting to a zero-count in order to begin the next sample. The figure below shows an illustration of a unipolar counter-type ADC.

This design suffers from approximation-delay due to the inability to sample the analog signal during every clocking period. Below is a result of early PSPICE transient simulation results using a unipolar counter-type ADC.

(PSPICE Circuit for reference)

2.) Successive Approximation Register (SAR) ADC

The next design for our ADC is called a successive-approximation-register ADC. As the name implies, this type of ADC re-evaluates its after each clock pulse and decides whether it needs to count "UP" or "DOWN" to reach the present analog values it is attempting to capture.

This type of ADC tends to be preferential as it does not require a reset to zero after each clock pulse. Therefore, it can be used at higher-speed circuits and also with more rapidly-occurring analog signals.

This time let's start off by looking at the logic flowchart.

[SOURCE]

In our case, the conversion will never be "finished". Even if the load cell is unloaded, we will continue to "check" if the value has changed.

Shown below is a screengrab of the PSPICE simulation circuit. Each major "subsystem" within the schematic of the ADC is labeled accordingly.

Running a simple transient analysis yields the following plot:

The green plot is the "output" of our ADC. Each step can be quantified as a unique binary value. You will note the "spikes" on some of the corners of our converted signal. We won't go in depth on these since it exceeds the scope of this project. However, all that you need to know is that in a Digital to Analog Converter (DAC) often there is a glitch known as a "Major Carry" glitch. This is present in the way a R-2R ladder operates. It is so brief and small in size it does not affect the results of this experiment.

In order to visualize how "well" our ADC is working, if we feed our digital-approximated wave back into a really, really lowpass filter (LPF) we can visually see (what we hope) is a close representation of our "original" analog signal. Here, we see the dark blue wave as out test analog signal, and the light blue wave as a reproduction of that wave, lagging by a little time (conversion time).

Building and Testing

The first stage of testing the ADC was individually testing each 4-bit binary counter IC to ensure correct operation as expected from developed testing plans and control logic programming.

NOTE: The off-shelf counter LS191 ICs selected for this design are only available in the SOIC-8 package which is not breadboard compatible. Therefore, it is necessary to first solder the SOIC-8 package counters to a “breakout board” with a breadboard-compatible header-pin layout.

The set of three LS191 counter ICs (4-bit counter ICs) totals 12-bits of available logic as per datasheet specification for cascaded operation of the LS191. Testing one IC requires soldering the SOIC-8 chip to a breakout board, and following the schematic in appendix A. To test one counter IC, one may simply ignore any carry-out / cascade operations.

Following this procedure, each LS191 IC was individually tested and reflected a successful test result such that each (4-bit) LS191 IC counted in binary-sequence from the (decimal equivalent) 0 to 7.