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Improved Raspberry-Pi RGB Matrix Driver

Use Raspberry-Pi DPI hardware to drive four chains of RGB LED panels.

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Custom driver board for HUB75, HUB75E, and Qiangli RGB panels. An Atmel XMEGA generates PWM, ABCDE, and LAT signals, while the raspberry-pi DPI generates the pixel clock and pixel data.

Uses Raspberry Pi DPI operating with 32MHz pixel clock.  (32MHz is the clock limit of the XMega)

  • Provides consistent panel timing regardless of CPU load.
  • Capable of drive large arrays with high refresh rate.
  • Software driver derives array dimensions from Linux framebuffer device, pwm bits, and panel type.
  • Panel CLK is produced by simple AND gate using pixel clock and DEN signal.

An Atmel XMega uses the pixel clock as it's external clock for synchronization.

  • Use HSYNC edge to capture scan line data from first few bytes of each scan line.
  • Generates PWM signal
  • Outputs row select bits
  • Generates LAT signal

Current Panel Configuration:

  • 48 Qiangli Q3F32 v4.1 panels (64 x 64, not hub75 compliant)
  • Canvas size: 768x256
  • Refresh Rate: 82Hz
  • Max OE active time: 49% at full brightness

driver3.sch

board schematic

sch - 646.65 kB - 02/26/2020 at 23:51

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driver3.brd

board layout

brd - 173.69 kB - 02/26/2020 at 23:51

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  • 1 × SN74LVC1G08DBVRE4 2-input AND gate
  • 2 × 74ABT16244ADL,112 4x 4-bit buffers with TTL inputs
  • 1 × 0402 330 Ohm Resistor
  • 1 × 0805 SMD LED
  • 11 × 0402 100nF Ceramic Capacitor

View all 8 components

  • New Circuit Boards

    Robert Rouquette03/09/2020 at 16:17 0 comments

    Received the new circuit boards today.

    Just need to populate them and verify the software updates.

  • Qiangli Q3F32 v4.1

    Robert Rouquette02/25/2020 at 23:48 0 comments

    The panels use the SM5266PH row select ICs.  These ICs are shift register based and make the panels incompatible with standard HUB75E ABCDE addressing.  The working panel pinout is as follows:

    • A - shift register clock, positive edge, should be clocked every row
    • B - shift register data, high -> row on, low -> row off, should set to high every eight row
    • C - blanking, timing/purpose unknown, should be kept low to enable outputs
    • D - async output enable, should be set to 3rd address bit
    • E - async output enable, should be set to 4th address bit

View all 2 project logs

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