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MIKBUG with 56K of SRAM

A project log for MIKBUG on Multicomp

MIKBUG Running on Multicomp with 6800 CPU

land-boardscomland-boards.com 06/25/2020 at 19:560 Comments

The EP2C5-DB card has 128KB of SRAM external to the FPGA. I wanted to get access to more of that SRAM. There were a couple of things in the way. Getting to 32KB was easy. To get past the 32KB limit I needed to move the MIKBUG I/O up in the memory space. I also needed to move the ROM up to the top of RAM. 

M6800_MIKBUG - Tested/Works

Memory Map

Changing MIKBUG ROM Location

I am using the a68 assembler to assemble code to a S-record file and the S-Record utilities to re-shift the address of the assembled S-Record down to the state of the ROM as well as create the HEX file needed by Quartus. The ROM monitor source code is V2_DIS_corrected.ASM.

The commands are:

a68 V2_DIS_corrected.ASM -l V2_DIS_corrected.LST -s smithbug.s
srec_cat smithbug.s -offset - -minimum-addr smithbug.s -o smithbug.hex -Intel

The output file, smithbug.hex is then copied into the Multicomp ROMs location. Next run Multicomp and select Processing then Update Memory Initialization File. If you get a warning at this point of when you build the FPGA programming file double click the end delete the highlighted (next to the last line) in the hex file and save. Re-build at that point and the error will go away.

Note than any code you have which relies on fixed locations for the MIKBUG ROM routines will need to be updated to use the new addresses. The listing file, V2_DIS_corrected.LST, contains the listing from the assembler output.

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