Replace SmithBUG with FigForth ROM

figFORTH can be loaded into ROM in the build instead of the SmithBUG ROM. The reset vector has to point to the FigForth COLD Start.

Memory Map

0x0000-0x0FFF - 4KB SRAM
0x1000-0x2FFF - 6K ROM (using 8KB entity, but only using 6KB)
0x3000-0x3FFF - 4KB SRAM
0x4000-0x7FFF - 16KB SRAM
0xFC00-0xFCFF - I/O Space
0xFFFE-0xFFFF - ROM start vector (physically top of the 8KB ROM)

Assemble

Assemble fig-Forth code using A68 Assembler.

"..\..\A68 6800 Assembler\a68.exe" fig-FORTH_6800.asm -l fig-FORTH_6800.lst -s fig-FORTH_6800.s

Manually delete top lines in S record file. After deleting, top lines should be:

S1131000017E1FA3017E1FD3680000000000007F43
S113101001000F300FFE0F30001F00000183018319

This matches the source:

   1000   01            ORIG    nop
   1001   7e 1f a3          jmp    CENT
                        ;**************************
                        ;*  W A R M   E N T R Y  **
                        ;**************************
   1004   01                nop
   1005   7e 1f d3          jmp    WENT    ;warm-sta a rt code, keeps current dictionary intact

Use srec_cat to shift addresses down and make Hex file:

srec_cat fig-FORTH_6800.s -offset - -minimum-addr fig-FORTH_6800.s -o fig-FORTH_6800.hex -Intel

Clone FPGA Folder

Archived M6800_MIKBUG_20220427.qar the project as it currently is since it's working well, as-is. Put into new folder and set new entity name (M6800_figForth). Tested as-is and it built/worked.

Update FPGA Entity

Bunch of stuff to do.

• Set up memories
  • Add address selects

w_SRAMAdr_1 <= '1'     when  w_cpuAddress(15 downto 12) = x"0" else
           '0';
w_SRAMAdr_2 <= '1'     when  w_cpuAddress(15 downto 12) = x"3" else
           '0';
w_SRAMAdr_3 <= '1'     when  w_cpuAddress(15 downto 14) = "01" else
           '0';
w_ROMAdr    <= '1'    when    w_cpuAddress(15 downto 12) = x"1" else
           '1'    when    w_cpuAddress(15 downto 12) = x"2" else
           '0';

•  Add SRAM entities (2 of 4KB, 1 of 16KB SRAM blocks from Common VHDL folder)
  • No output q latch
• Add 8KB FigForth ROM entity
  • No output q latch
• Add reset vector "manually" to read data multiplexer (0xFFFE-0xFFFF = 0x1000)

      -- ____________________________________________________________________________________
      -- CPU Read Data multiplexer
      w_cpuDataIn <=
          io_extSRamData    when w_extSRAM = '1'           else    -- External SRAM (0xA000-0xDFFF)
                  ...
          x"10"             when w_cpuAddress = x"FFFE"    else    -- Reset vector Upper ($1000)
          x"00"             when w_cpuAddress = x"FFFF"    else    -- Reset vector Lower
          w_romData         when w_ROMAdr = '1'            else    -- ROM
  

Create FPGA .jic file and Download

Runs!!!

Saved M6800_FigForth_20220427.qar archive file.

Issues

Output looks good on Serial port, but tabbed? over in VDU.