After my mistake with bridging the outputs of a 3 to 8 decoder I have been taking another look at the address logic. I believe that I can use OR and NOT gates to do the selection between the ROM RAM and peripherals. I have come up with this. I still have to check it with a logicsim but seems it sane. the nice thing is I can use some of the spare NOT gates for the Q and A15 inverters so extra bonus.