Good things first, the device is ideal for the scenario described in the first log of the project. This device is an ideal choice, when it is necessary to determine which pin of the FPGA is connected to a contact pad reached by Probe Pin on the PCB. For this case, the speed of the JTAG interface software emulation is enough. The only drawback in this case is that we get the bit number in the Boundary Scan Register, which must be converted to the pin name with the BSDL file.
The way of working of EXTEST, EXTEST_PULSE, EXTEST_TRAIN commands suggest that the Boundary Scan Register will be initialized with a sufficiently large number of test vectors, followed by a comparison of the results. Since JTAG software emulation is used, the speed of operation is much lower than the max permissible, which is usually about 10 MHz.
It should also be noted that the limited Atmega328p memory capacity makes introduction of some new features impossible.
If the project is going to be developed in the future, the hardware would be implemented on STLINK-V3. There are few reasons why. Firstly, it is very affordable and costs less than 10 USD, secondly, it contains a powerful microcontroller STM32F723 .