After building the initial circuit for the VDC-II "chip" (a TinyFPGA BX programmed with the VDC-II core in progress), I was greatly disappointed to learn that it did not work once I placed the FPGA in-circuit. Until that point, everything worked great. But, once the FPGA was in-circuit, the level shifters started to behave with wild abandon. So much so, in fact, that the RC2014 computer I'm using refused to boot.
The data bus had wild, 50-52MHz oscillations on them, crazy amounts of overshoot and undershoot at times, and you can clearly see where the one-shot circuits of the level shifters would start and stop. All in all, the logic levels were not clean, and I'm convinced the Z80 and/or memory on the bus refused to have anything to do with this nonsense.
Here's the schematic (PDF) of the current circuit.
After taking the TinyFPGA BX out of the circuit, I decided to just test it by hand, the good old fashioned way: strap a bunch of pull-down resistors on all inputs, and selectively use wires to +3.3V to raise them high when needed. I'm happy to report that, as I type this, the VDC-II core (such as it is) seems to be able to accept and return bytes via the Z80-side of the interface.
In theory, I could have programmed the chip sufficiently to actually start generating an HSYNC signal. However, I didn't bother going this far; manipulating the bus interface by pulling and setting wires in the breadboard was terribly exhausting on its own. Maybe tomorrow; or, I'll just wait for the new level shifters to arrive instead.